adv7342 Analog Devices, Inc., adv7342 Datasheet
adv7342
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adv7342 Summary of contents
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... One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs ADV7342/ADV7343 ) and phase SC 2 C® and SPI® compatibility SFL/ V AGND MISO AA ADV7342/ADV7343 11-BIT DAC 1 YUV 16× TO FILTER 11-BIT YCrCb/ DAC 2 RGB 11-BIT 16× FILTER DAC 3 ...
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... ADV7342/ADV7343 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Detailed Features .............................................................................. 4 General Description ......................................................................... 4 Specifications..................................................................................... 5 Power Supply and Voltage Specifications.................................. 5 Voltage Reference Specifications ................................................ 5 Input Clock Specifications .......................................................... 5 Analog Output Specifications..................................................... 6 Digital Input/Output Specifications........................................... 6 Digital Timing Specifications ..................................................... 7 MPU Port Timing Specifications ............................................... 8 Power Specifications .................................................................... 8 Video Performance Specifications ...
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... ED/HD Test Patterns ..................................................................74 Appendix 5—SD Timing................................................................75 Appendix 6—HD Timing ..............................................................80 Appendix 7—Video Output Levels...............................................81 REVISION HISTORY 10/06—Revision 0: Initial Version SD YPrPb Output Levels—SMPTE/EBU N10........................81 ED/HD YPrPb Output Levels ...................................................82 SD/ED/HD RGB Output Levels................................................83 SD Output Plots ..........................................................................84 Appendix 8—Video Standards ......................................................85 Outline Dimensions........................................................................87 Ordering Guide ...........................................................................87 Rev Page ADV7342/ADV7343 ...
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... Video (Y/C), and component (YPrPb/RGB) analog outputs in either standard definition (SD), enhanced definition (ED), or high definition (HD) video formats. The ADV7342/ADV7343 each have a 24-bit pixel input port that can be configured in a variety of ways. SD video formats are supported over a SDR interface and ED/HD video formats are supported over SDR and DDR interfaces. Pixel data can be supplied in either the YCrCb or RGB color spaces ...
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... SD = standard definition enhanced definition (525p/625p high definition. Conditions Conditions . REF = 2 3.465 2. 3. DD_IO Conditions 1 Min Typ SD/ (at 54 MHz 74. 74. Rev Page ADV7342/ADV7343 Min Typ Max 1.71 1.8 1.89 2.97 3.3 3.63 1.71 1.8 1.89 2.6 3.3 3.465 0.002 Min Typ Max 1.186 1.248 1.31 1.15 1.235 1.31 ±10 Max Unit MHz ...
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... ADV7342/ADV7343 ANALOG OUTPUT SPECIFICATIONS All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 5. Parameter 1 Full-Drive Output Current (Full-Scale) 2 Low Drive Output Current (Full-Scale) DAC-to-DAC Matching Output Compliance Output Capacitance, C OUT ...
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... SD ED/HD-SDR or ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) SD ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) SD oversampling disabled SD oversampling enabled SD oversampling disabled SD oversampling enabled ED oversampling disabled ED oversampling enabled HD oversampling disabled HD oversampling enabled Rev Page ADV7342/ADV7343 Min Typ Max Unit 2.1 ns 2.3 ns 2.3 ns 1.7 ns 1 ...
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... ADV7342/ADV7343 MPU PORT TIMING SPECIFICATIONS All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 8. Parameter 2 1 MPU PORT MODE SCL Frequency SCL High Pulse Width SCL Low Pulse Width Hold Time (Start Condition), t ...
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... SET1 4.12 kΩ 300 Ω SET2 510 kΩ 37.5 Ω SET1 4.12 kΩ 300 Ω SET2 L2 NTSC NTSC Luma ramp Flat field full bandwidth Rev Page ADV7342/ADV7343 Min Typ Max Unit 11 Bits 0.4 LSBs 0.5 LSBs 0.15 LSBs 0.5 LSBs 0.25 LSBs 0.2 LSBs 0.5 ±% 0.5 % ...
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... C0* CONTROL OUTPUTS *SELECTED BY SUBADDRESS 0x01, BIT 7. CLKIN_A S_HSYNC, CONTROL INPUTS S_VSYNC CONTROL OUTPUTS • • In addition, refer to Table 31 for the ADV7342/ADV7343 input configuration Cr0 Y1 Cb2 Figure 2. SD Only, 8-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000) ...
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... Figure 7. ED/HD-SDR Only, 24-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 001) Rev Page Cb2 Cr2 Cb4 Cr4 Cb2 Cb3 Cb4 Cb5 Cr2 Cr3 Cr4 Cr5 ADV7342/ADV7343 ...
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... ADV7342/ADV7343 CONTROL INPUTS *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. Figure 8. ED/HD-DDR Only, 8-Bit, 4:2:2 YCrCb ( HSYNC / VSYNC ) Pixel Input Mode (Input Mode 010) CLKIN_A CONTROL OUTPUTS *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. Figure 9. ED/HD-DDR Only, 8-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 010) ...
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... CONTROL OUTPUTS Figure 13. ED Only (at 54 MHz), 8-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 111) EH/HD INPUT Y1 Cb2 Y2 Cr2 Cr0 Y1 Cb2 Y2 Cr2 Cr0 Y1 Cb2 Cb0 Y0 Cr0 Rev Page ADV7342/ADV7343 SD INPUT Cr2 Y1 ...
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... ADV7342/ADV7343 Y OUTPUT P_HSYNC P_VSYNC P_BLANK AND b AS PER RELEVANT STANDARD PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY ...
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... SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Figure 17. HD-DDR, 8-Bit, 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram Cb0 b b Rev Page ADV7342/ADV7343 Cr0 Cb2 Cr2 ...
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... ADV7342/ADV7343 S_HSYNC S_VSYNC Y7 TO Y0* *SELECTED BY SUBADDRESS 0x01, BIT 7. SDA SCL SPI_SS SCLK t 5 MOSI MISO Figure 18. SD Input Timing Diagram (Timing Mode Figure 19. MPU Port Timing Diagram (I ...
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... Values are based on a JEDEC 4 layer test board. −0 +0.3 V The ADV7342/ADV7343 are Pb-free products. The lead finish is −0 +0.3 V 100% pure Sn electroplate. The devices are RoHS compliant, −0 +0.3 V suitable for Pb-free applications up to 255°C (±5°C) IR reflow − ...
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... I 48 SFL/MISO I SET1 PIN ADV7342/ADV7343 7 TOP VIEW 8 (Not to Scale Figure 21. Pin Configuration Description 8-Bit Pixel Port the LSB. Refer to Table 31 for input modes. ...
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... GND_IO enhanced definition = 525p and 625p. 2 LSB = least significant bit. In the ADV7342, setting the LSB to 0 sets the I 2 LSB to 0 sets the I C address to 0x54. Setting sets the I Description This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 kΩ ...
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... ADV7342/ADV7343 TYPICAL PERFORMANCE CHARACTERISTICS ED Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) Figure 22. ED 8× Oversampling, PrPb Filter (Linear) Response ED Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 – ...
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... Rev Page ADV7342/ADV7343 FREQUENCY (MHz) Figure 31. SD PAL, Luma Low-Pass Filter Response FREQUENCY (MHz) Figure 32. SD NTSC, Luma Notch Filter Response ...
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... ADV7342/ADV7343 Y RESPONSE IN SD OVERSAMPLING MODE 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) Figure 34. SD, 16× Oversampling, Y Filter Response 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 35. SD Luma SSAF Filter Response MHz ...
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... Figure 44. SD Chroma 1.0 MHz Low-Pass Filter Response 0 –10 –20 –30 –40 –50 –60 – Figure 45. SD Chroma 0.65 MHz Low-Pass Filter Response Rev Page ADV7342/ADV7343 FREQUENCY (MHz FREQUENCY (MHz FREQUENCY (MHz) ...
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... ADV7342/ADV7343 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 46. SD Chroma CIF Low-Pass Filter Response Rev Page –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 47. SD Chroma QCIF Low-Pass Filter Response ...
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... C-compatible) The ADV7342/ADV7343 act as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/ W bit. It interprets the first byte as the device address and the second byte as the starting subaddress ...
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... ADV7342/ADV7343, MSB first, on the MOSI line immediately after the starting subaddress. The data bytes are clocked into the ADV7342/ADV7343 on the rising edge of SCLK. When all data bytes have been written, the master completes the transfer by driving and holding the ALSB/ SPI_SS pin high. ...
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... REGISTER MAP ACCESS A microprocessor can read from or write to all registers of the ADV7342/ADV7343 via the MPU port, except for registers that are specified as read-only or write-only registers. The subaddress register determines which register the next read or write operation accesses. All communication through the MPU port starts with an access to the subaddress register. ...
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... ADV7342/ADV7343 Table 15. Register 0x01 to Register 0x09 SR7 to SR0 Register Bit Description 0x01 Mode Select Reserved. Register DDR Clock Edge Alignment. Note: Only used for ED HD DDR modes. Reserved. Input Mode. Note: See Reg. 0x30, Bits[7:3] for ED/HD format selection. Y/C/S Bus Swap. 0x02 Mode Reserved ...
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... Rev Page ADV7342/ADV7343 Reset 1 0 Register Setting Value 0x00 0 1 +0.018 +0.036% … … … +7.382 +7. −7. −7.382% ...
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... ADV7342/ADV7343 Table 17. Register 0x12 to Register 0x17 SR7 to SR0 Register 0x12 Pixel Port Readback (S Bus) 0x13 Pixel Port Readback (Y Bus) 0x14 Pixel Port Readback (C Bus) 0x16 Control Port Readback 0x17 Software Reset Bit Number Bit Description S[7:0] Readback Y[7:0] Readback. ...
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... SMPTE 274M- SMPTE 274M-10, SMPTE 274M-11 ITU-R BT.709-5. 10011–11111 Reserved. Rev Page ADV7342/ADV7343 Reset Note Value ED 0x00 HD 1 525p @ 59.94 Hz 525p @ 59.94 Hz 625p @ 50 Hz 625p @ 50 Hz 720p @ 60/59.94 Hz 720p @ 50 Hz 720p @ 30/29.97 Hz 720p @ 25 Hz 720p @ 24/23.98 Hz 1035i @ 60/59.94 Hz 1080i @ 30/29.97 Hz 1080i @ 25 Hz 1080p @ 0/29 ...
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... ADV7342/ADV7343 Table 19. Register 0x31 to Register 0x33 SR7 to SR0 Register Bit Description 0x31 ED/HD Mode ED/HD Pixel Data Valid. Register 2 Reserved. ED/HD Test Pattern Enable. ED/HD Test Pattern Hatch/Field. ED/HD VBI Open. ED/HD Undershoot Limiter. ED/HD Sharpness Filter. 0x32 ED/HD Mode ED/HD Y Delay with Respect to Falling Register 3 Edge of HSYNC. ED/HD Color Delay with Respect to Falling Edge of HSYNC ...
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... Field/line counter free running Disabled. 1 Enabled. 0 Disabled. 1 Enabled. 0 DAC 2 = Pb, DAC 3 = Pr. 1 DAC 2 = Pr, DAC 3 = Pb. 0 Gamma Correction Curve A. 1 Gamma Correction Curve B. 0 Disabled. 1 Enabled. 0 Mode A. 1 Mode B. 0 Disabled. 1 Enabled. Rev Page ADV7342/ADV7343 Reset Value 0x48 Table 51 ). Table 52 ). 0x00 ...
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... ADV7342/ADV7343 Table 21. Register 0x36 to Register 0x43 SR7 to SR0 Register Bit Description 1 0x36 ED/HD Y Level ED/HD Test Pattern Y Level. 1 0x37 ED/HD Cr Level ED/HD Test Pattern Cr Level. 1 0x38 ED/HD Cb Level ED/HD Test Pattern Cb Level. 0x39 ED/HD Mode Reserved. Register 7 ED/HD EIA/CEA-861B Synchronization Compliance. Reserved. 0x40 ED/HD Sharpness ED/HD Sharpness Filter Gain, Filter Gain Value A ...
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... ED/HD Adaptive Filter Gain 3, Value A. ED/HD Adaptive Filter Gain 3, 0 Value B. 0 … … 1 ED/HD Adaptive Filter Threshold A. x ED/HD Adaptive Filter Threshold B. x ED/HD Adaptive Filter Threshold C. x Rev Page ADV7342/ADV7343 Bit Number Register Setting Gain ...
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... ADV7342/ADV7343 Table 24. Register 0x5E to Register 0x6E SR7 to SR0 Register Bit Description 0x5E ED/HD CGMS Type B ED/HD CGMS Type B Register 0 Enable. ED/HD CGMS Type B CRC Enable. ED/HD CGMS Type B Header Bits. 0x5F ED/HD CGMS Type B ED/HD CGMS Type B Register 1 Data Bits. 0x60 ED/HD CGMS Type B ED/HD CGMS Type B Register 2 Data Bits. ...
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... Closed captioning disabled Closed captioning on odd field only Closed captioning on even field only Closed captioning on both fields. 0 Reserved. Rev Page ADV7342/ADV7343 Reset Value 0x10 0x0B Table 32 in the Output section. Table 32 in the Output section. 0x04 ...
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... ADV7342/ADV7343 Table 26. Register 0x84 to Register 0x89 SR7 to SR0 Register Bit Description 0x84 SD Mode SD VSYNC-3H. Register 4 SD SFL/SCR/TR Mode Select. SD Active Video Length. SD Chroma. SD Burst. SD Color Bars. SD Luma/Chroma Swap. 0x86 SD Mode NTSC Color Subcarrier Adjust (Delay Register 5 from the falling edge of output HSYNC pulse to start of color burst) ...
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... Disabled −11 IRE −6 IRE −1.5 IRE must be written to this bit. 0 Disabled. 1 Enabled Disabled clock cycles clock cycles Reserved must be written to these bits. Rev Page ADV7342/ADV7343 Reset Value 0x00 0x00 ...
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... ADV7342/ADV7343 Table 27. Register 0x8A to Register 0x98 SR7 to SR0 Register Bit Description 0x8A SD Timing Register 0 SD Slave/Master Mode. SD Timing Mode. Reserved. SD Luma Delay. SD Minimum Luma Value. SD Timing Reset. 0x8B SD Timing Register 1 SD HSYNC Width. (Note: Applicable in master modes only, that is, Subaddress 0x8A, Bit HSYNC to VSYNC Delay ...
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... Rev Page ADV7342/ADV7343 Register Setting CGMS Data Bits[C19:C16] Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled CGMS Data Bits[C13:C8] or WSS Data Bits[W13:W8] ...
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... ADV7342/ADV7343 SR7 to SR0 Register Bit Description 0xA4 SD DNR 1 DNR Threshold. Border Area. Block Size Control. 0xA5 SD DNR 2 DNR Input Select. DNR Mode. DNR Block Offset. Table 29. Register 0xA6 to Register 0xBB SR7 to SR0 Register Bit Description 0xA6 SD Gamma Gamma Curve A (Point 24). ...
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... Macrovision MV Control Bits. 0xED Macrovision MV Control Bits. 0xEE Macrovision MV Control Bits. 0xEF Macrovision MV Control Bits. 0xF0 Macrovision MV Control Bits. 0xF1 Macrovision MV Control Bit. 1 Macrovision registers are available on the ADV7342 only. Bit Number ...
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... ADV7342/ADV7343 INPUT CONFIGURATION The ADV7342/ADV7343 support a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7342/ADV7343 default to standard definition only (SD only) upon power-up. Table 31 provides an overview of all possible input configurations. Each input mode is described in detail in the following sections. ...
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... C0 are the respective bus LSBs. SIMULTANEOUS STANDARD DEFINITION AND ENHANCED DEFINITION/HIGH DEFINITION Subaddress 0x01, Bits[6:4] = 011 or 100 The ADV7342/ADV7343 are able to simultaneously process SD 4:2:2 YCrCb data and ED/HD 4:2:2 YCrCb data. The 27 MHz SD clock signal must be provided on the CLKIN_A pin. The ED/HD clock signal must be provided on the CLKIN_B pin. SD input synchronization signals are provided on the S_HSYNC and S_VSYNC pins ...
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... The interleaved pixel data is input on Pin Y7 to Pin Y0, with Y0 being the LSB. CLKIN_A Y[7:0] 3FF 00 Figure 57. ED Only (at 54 MHz) Input Sequence (EAV/SAV) MPEG2 DECO DER 54MHz YCrCb YCrCb INTERLACED TO PROGRESSIVE Figure 58. ED Only (at 54 MHz) Example Application Rev Page Cb0 Y0 Cr0 Y1 CLKIN_A ADV7342/ ADV7343 10 Y[7:0] P_VSYNC, 3 P_HSYNC, P_BLANK ...
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... OUTPUT CONFIGURATION The ADV7342/ADV7343 support a number of different output configurations. Table 32 to Table 35 lists all possible output configurations. Table 32. SD Only Output Configurations RGB/YPrPb SD DAC SD DAC Output Select 1 Output 2 Output 1 (0x02, Bit 5) (0x82, Bit 2) (0x82, Bit ...
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... Subaddress 0x30, Bits[7:3] = 00001 For any ED/HD input data that does not conform to the standards available in the ED/HD input mode table (Subaddress 0x30, Bits[7:3]), the ED/HD nonstandard timing mode can be used to interface to the ADV7342/ADV7343. Table 36. Output Oversampling Modes and Rates Input Mode Subaddress 0x01 [6:4] ...
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... Subaddress 0xBB can be used to identify the number of the active field. Subcarrier Frequency Lock (SFL) Mode In this mode (Subaddress 0x84, Bits[2:1] = 11), the ADV7342 /ADV7343 can be used to lock to an external video source. The SFL mode allows the ADV7342/ADV7343 to automatically alter the subcarrier frequency to compensate for line length variations ...
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... COUNT START 128 RTC TIME SLOT 01 1 FOR EXAMPLE, VCR OR CABLE PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7342/ADV7343 PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS SEQUENCE BIT PAL LINE NORMAL LINE INVERTED NTSC CHANGE 4 RESET ADV7342/ADV7343 DDS ...
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... SD SQUARE PIXEL MODE 0xCB 0x8A Subaddress 0x82, Bit 4 0x09 The ADV7342/ADV7343 can be used to operate in square pixel 0x2A mode (Subaddress 0x82, Bit 4). For NTSC operation, an input clock of 24.5454 MHz is required. Alternatively, for PAL operation, an input clock of 29.5 MHz is required. The internal timing logic adjusts accordingly for square pixel mode operation ...
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... The desired response can be programmed using Subaddress 0xA2. The variation of frequency responses is shown in Figure 36 to Figure 38. In addition to the chroma filters listed in Table 39, the ADV7342/ ADV7343 contain an SSAF filter specifically designed for the color difference component outputs, Pr and Pb. This filter has a cutoff frequency of ~2.7 MHz and a gain of – ...
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... ED/HD Sinc Compensation Filter Response Subaddress 0x33, Bit 3 The ADV7342/ADV7343 include a filter designed to counter the effect of sinc roll-off in DAC 1, DAC 2, and DAC 3 while operating in ED/HD mode. This filter is enabled by default. It can be disabled using Subaddress 0x33, Bit 3. The benefit of the filter is illustrated in Figure 66 and Figure 67. ...
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... ADV7342/ADV7343 If RGB output is selected, the ED/HD CSC matrix scalar uses the following equations × × × Y − × Pb) − × Pr × × Pb Note that subtractions are implemented in hardware. If YPrPb output is selected, the following equations are used × × ...
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... The ADV7342/ADV7343 provide a range of ±22.5° in increments of 0.17578125°. For normal operation (zero adjustment), this register is set to 0x80. Values 0xFF and 0x00 represent the upper and lower limits, respectively, of the attainable adjustment in NTSC mode ...
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... ADV7342/ADV7343 DOUBLE BUFFERING Subaddress 0x33, Bit 7 for ED/HD, Subaddress 0x88, Bit 2 for SD Double-buffered registers are updated once per field. Double buffering improves overall performance, because modifications to register settings are not made during active video, but take effect prior to the start of the active video on the next field. ...
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... The gamma curves in Figure 70 and Figure 71 are examples only; any user-defined curve in the range from 16 to 240 is acceptable. 300 250 200 150 100 50 200 250 0 0 Figure 71. Signal Input (Ramp) and Selectable Output Curves Rev Page ADV7342/ADV7343 γ ⎞ − ⎛ ⎞ ⎟ × − + ⎜ ⎟ ...
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... ADV7342/ADV7343 ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS Subaddress 0x40, Subaddress 0x58 to Subaddress 0x5D There are three filter modes available on the ADV7342/ADV7343: a sharpness filter mode and two adaptive filter modes. ED/HD Sharpness Filter Mode To enhance or attenuate the Y signal in the frequency ranges shown in Figure 72, the ED/HD sharpness filter must be enabled (Subaddress 0x31, Bit 7) and the ED/HD adaptive filter must be disabled (Subaddress 0x35, Bit 7) ...
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... Reference 0x01 0x02 0x30 0x31 0x35 0x40 0x58 a 0x59 b 0x5A c 0x5B d 0x5C e 0x5D f Rev Page ADV7342/ADV7343 M 4.00µs CH1 ALL FIELDS 500mV 4.00µs 1 9.99978ms Register Setting 0xFC 0x38 0x20 0x00 0x81 0x80 0x00 0xAC 0x9A 0x88 0x28 0x3F 0x64 Figure 75. Output Signal from ED/HD Adaptive Filter (Mode A) ...
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... ADV7342/ADV7343 When changing the adaptive filter mode to Mode B (Subaddress 0x35, Bit 6), the output shown in Figure 76 can be obtained. Figure 76. Output Signal from ED/HD Adaptive Filter (Mode B) SD DIGITAL NOISE REDUCTION Subaddress 0xA3 to Subaddress 0xA5 Digital noise reduction (DNR) is applied to the Y data only. A filter block selects the high frequency, low amplitude compo- nents of the incoming signal (DNR input select) ...
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... SD ACTIVE VIDEO EDGE CONTROL Subaddress 0x82, Bit 7 The ADV7342/ADV7343 are able to control fast rising and 8 × 8 PIXEL BLOCK falling signals at the start and end of active video in order to minimize ringing. ...
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... ADV7342/ADV7343 LUMA CHANNEL WITH ACTIVE VIDEO EDGE DISABLED 100 IRE 0 IRE VOLTS IRE:FLT 0 VOLTS IRE:FLT 0.5 0 –2 LUMA CHANNEL WITH ACTIVE VIDEO EDGE ENABLED 100 IRE 87.5 IRE 50 IRE 12.5 IRE 0 IRE Figure 81. Example of Active Video Edge Functionality 100 L135 – Figure 82 ...
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... EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL For timing synchronization purposes, the ADV7342/ADV7343 are able to accept either EAV/SAV time codes embedded in the input pixel data or external synchronization signals provided on the S_HSYNC , S_VSYNC , P_HSYNC , P_VSYNC , and P_BLANK pins (see Table 49 also possible to output synchronization signals on the S_HSYNC and S_VSYNC pins (see Table 50 to Table 52). ...
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... When using this feature, a clock signal should be applied to the CLKIN_A pin to register the levels applied to the input pins. RESET MECHANISM Subaddress 0x17, Bit 1 The ADV7342/ADV7343 have a software reset accessible via 2 the I C/SPI MPU port. A software reset is activated by writing Subaddress 0x17, Bit 1. This resets all registers to their default values ...
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... V pin. For optimal performance, an external voltage REF reference such as the AD1580 should be used with the ADV7342/ ADV7343 external voltage reference is not used, a 0.1 μF capacitor should be connected from the V VIDEO OUTPUT BUFFER AND OPTIONAL ...
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... The external loop filter components and components connected 14n to the COMP, V 240 PHASE 12n possible to and on the same side of the PCB as the ADV7342/ (Degrees) 160 ADV7343. Adding vias to the PCB to get the components closer 10n 80 to the ADV7342/ADV7343 are not recommended. ...
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... The DAC output traces should be kept as short as possible. The termination resistors on the DAC output traces should be placed as close as possible to and on the same side of the PCB as the ADV7342/ADV7343. To avoid crosstalk between the DAC outputs recom- mended that as much space as possible be left between the traces connected to the DAC output pins ...
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... NOTES 1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED TO THE COMP AND DAC OUTPUT PINS SHOULD BE LOCATED SET REF CLOSE TO AND ON THE SAME SIDE OF THE PCB AS THE ADV7342/ADV7343. 2. WHEN OPERATING MODE, THE DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB/SPI_SS PIN: ...
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... Line 283 of even fields. Subaddress 0x99, Bits[6:5] control whether CGMS data is output on odd or even fields or both. SD CGMS data can only be transmitted when the ADV7342/ ADV7343 are configured in NTSC mode. The CGMS data is 20 bits long. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit (see Figure 91) ...
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... ADV7342/ADV7343 +100 IRE +70 IRE 0 IRE –40 IRE 11.2µs +700mV 70% ± 10% 0mV –300mV 5.8µs ± 0.15µs 6T PEAK WHITE 500mV ± 25mV SYNC LEVEL 5.5µs ± 0.125µs +700mV 70% ± 10% 0mV –300mV 4T 3.128µs ± 90ns REF C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 49.1µ ...
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... Rev Page ADV7342/ADV7343 CRC SEQUENCE BIT 20 × 2200/77) = 1.038µs H CRC SEQUENCE BIT 134 P122 P123 P124 P125 P126 P127 CRC SEQUENCE BIT 134 . . P122 P123 P124 P125 P126 P127 ...
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... ADV7342/ADV7343 APPENDIX 2—SD WIDE SCREEN SIGNALING Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B The ADV7342/ADV7343 support wide screen signaling (WSS) conforming to the ETSI 300 294 standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the device is configured in PAL mode. The WSS data is 14 bits long ...
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... The FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Line 21 and Line 284. The ADV7342/ADV7343 use a single buffering method. This means that the closed captioning buffer is only 1-byte deep. Therefore, there is no frame delay in outputting the closed captioning data, unlike other 2-byte deep buffering systems ...
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... ADV7342/ADV7343 APPENDIX 4—INTERNAL TEST PATTERN GENERATION SD TEST PATTERNS The ADV7342/ADV7343 are able to generate SD color bar and black bar test patterns. The register settings in Table 56 are used to generate an SD NTSC 75% color bar test pattern. CVBS output is available on DAC 4, S-Video (Y/C) output is on DAC 5 and DAC 6, and YPrPb output is on DAC 1 to DAC 3 ...
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... END OF ACTIVE VIDEO LINE Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = The ADV7342/ADV7343 generate H and F signals required for the SAV and EAV time codes in the CCIR656 standard. The H bit is output on S_HSYNC and the F bit is output on S_VSYNC . DISPLAY 522 ...
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... Mode 1—Slave Option (Subaddress 0x8A = this mode, the ADV7342/ADV7343 accept horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as per CCIR- 624 ...
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... Mode 1—Master Option (Subaddress 0x8A = this mode, the ADV7342/ADV7343 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as per CCIR-624 ...
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... VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The ADV7342/ADV7343 automatically blank all normally blank lines as per CCIR-624. HSYNC and VSYNC are output on the S_HSYNC and S_VSYNC pins, respectively. ...
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... In this mode, the ADV7342/ADV7343 accept or generate horizontal sync and odd/even field signals. When HSYNC is high, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as per CCIR-624. HSYNC and VSYNC are output in master mode and input in slave mode on the S_VSYNC and S_VSYNC pins, respectively ...
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... ADV7342/ADV7343 APPENDIX 6—HD TIMING FIELD 1 1124 1125 P_VSYNC P_HSYNC FIELD 2 561 562 P_VSYNC P_HSYNC VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 113. 1080i HSYNC and VSYNC Input Timing Rev Page ...
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... SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10 Pattern: 100% Color Bars 700mV 300mV Figure 114. Y Levels—NTSC 700mV Figure 115. Pr Levels—NTSC 700mV Figure 116. Pb Levels—NTSC 700mV 300mV Figure 117. Y Levels—PAL 700mV Figure 118. Pr Levels—PAL 700mV Figure 119. Pb Levels—PAL Rev Page ADV7342/ADV7343 ...
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... ADV7342/ADV7343 ED/HD YPrPb OUTPUT LEVELS EIA-770.2, STANDARD FOR Y INPUT CODE 940 64 EIA-770.2, STANDARD FOR Pr/Pb 960 512 64 Figure 120. EIA-770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 EIA-770.1, STANDARD FOR Pr/Pb 960 512 64 Figure 121. EIA-770.1 Standard Output Signals (525p/625p) INPUT CODE ...
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... Figure 125. SD/ED RGB Output Levels—RGB Sync Enabled R 700mV/525mV 300mV G 700mV/525mV 300mV B 700mV/525mV 300mV Figure 126. HD RGB Output Levels—RGB Sync Disabled R 700mV/525mV 600mV 300mV 0mV G 700mV/525mV 600mV 300mV 0mV B 700mV/525mV 600mV 300mV 0mV Figure 127. HD RGB Output Levels—RGB Sync Enabled Rev Page ADV7342/ADV7343 ...
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... ADV7342/ADV7343 SD OUTPUT PLOTS VOLTS IRE:FLT 100 0 –50 L76 MICROSECONDS APL = 44.5% PRECISION MODE OFF 525 LINE NTSC SYNCHRONOUS SYNC = A SLOW CLAMP TO 0.00V AT 6.72μs µ FRAMES SELECTED 1, 2 Figure 128. NTSC Color Bars (75%) VOLTS IRE:FLT 0.6 0 –0.2 F2 L238 ...
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... DATUM H DIGITAL HORIZONTAL BLANKING Figure 135. EAV/SAV Input Data Timing Diagram (SMPTE293M) VERTICAL BLANK Figure 136. SMPTE 293M (525p) Rev Page ADV7342/ADV7343 4T 1920T DIGITAL SAV CODE ACTIVE LINE ...
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... ADV7342/ADV7343 ACTIVE VIDEO 622 623 624 625 747 748 749 750 FIELD 1 1124 1125 FIELD 2 561 562 VERTICAL BLANK Figure 137. ITU-R BT.1358 (625p) VERTICAL BLANKING INTERVAL Figure 138. SMPTE 296M (720p) VERTICAL BLANKING INTERVAL ...
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... Figure 140. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters 1 Macrovision Antitaping Package Description Yes 64-Lead Low Profile Quad Flat Package [LQFP] No 64-Lead Low Profile Quad Flat Package [LQFP] Yes ADV7342 Evaluation Platform No ADV7343 Evaluation Platform Rev Page ADV7342/ADV7343 49 48 10.20 10. ...
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... ADV7342/ADV7343 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components system, provided that the system conforms to the I ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...