adv7401 Analog Devices, Inc., adv7401 Datasheet
adv7401
Available stocks
Related parts for adv7401
adv7401 Summary of contents
Page 1
... HD and SMPTE standards. Graphic digitization is also supported by the ADV7401 capable of digitizing RGB graphics signals from VGA to SXGA rates and converting them into a digital RGB or YCrCb pixel output stream. SCART and overlay functionality are enabled by the ADV7401’ ...
Page 2
... ADV7401 TABLE OF CONTENTS Functional Block Diagram .............................................................. 3 Electrical Characteristics ................................................................. 4 Video Specifications ......................................................................... 6 Timing Characteristics..................................................................... 7 Analog Specifications....................................................................... 8 Absolute Maximum Ratings............................................................ 9 Stress Ratings ................................................................................ 9 Package Thermal Performance................................................... 9 Thermal Specifications ................................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Timing Diagrams............................................................................ 12 Detailed Functionality ................................................................... 13 Analog Front End ....................................................................... 13 SDP Pixel Data Output Modes ................................................. 13 REVISION HISTORY 9/05— ...
Page 3
... FUNCTIONAL BLOCK DIAGRAM OUTPUT FIFO AND FORMATTER Figure. 1. Rev. SpA | Page ADV7401 ...
Page 4
... The min/max specifications are guaranteed over this range. 2 Temperature range −40°C to +85°C (0°C to 70°C temperature range for ADV7401KSTZ-140). MIN MAX 3 All specifications obtained using programming scripts with the following sequence included: Addr 0x0E - data 0x80, Addr 0x54 - data 0x00, Addr 0x0E - data 0x00. ...
Page 5
... Max INL and DNL specifications obtained with part configured for component video input. 6 Specification for ADV7401BSTZ-110 and ADV7401KSTZ-140 only. 7 Specification for ADV7401KSTZ-140 only. 8 Guaranteed by characterization obtain specified V level on Pin 38, Register 0x13 (wo) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00, ...
Page 6
... Luma Brightness Accuracy Luma Contrast Accuracy 1 The min/max specifications are guaranteed over this range. 2 Temperature range −40°C to +85°C (0°C to 70°C temperature range for ADV7401KSTZ-140). MIN MAX 3 Guaranteed by characterization. 4 Nominal sync depth is 300 mV at 100% sync depth range. ...
Page 7
... MAX 3 Guaranteed by characterization. 4 Maximum LLC1 frequency is 80 MHz for ADV7401BSTZ-80 and is 110 MHz for ADV7401BSTZ-110. 5 TTL input values are with rise/fall times ≤3 ns, measured between the 10% and 90% points. 6 SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4. ...
Page 8
... Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current 1 The min/max specifications are guaranteed over this range. 2 Temperature range −40°C to +85°C (0°C to 70°C temperature range for ADV7401KSTZ-140). MIN MAX 3 Guaranteed by characterization. 4 Except Pin 51 (FB). Test Conditions ...
Page 9
... Max (DVDDIO × IDVDDIO) + (PVDD × IPVDD)). Symbol Test Conditions θ 4-layer PCB with solid ground plane JC θ 4-layer PCB with solid ground plane (still air) JA Rev. SpA | Page ADV7401 ) of 125°C. This J MAX × Max Typ Unit 7 °C/W 30 °C/W ...
Page 10
... P22 to P29 44, 43, 21, 20, 45, 34 P1, P10 to P11, 100, 97, 96, 95, 88, 87, 84, 83 P20 to P21, P31 to P40 3 INT PIN 1 ADV7401 LQFP TOP VIEW (Not to Scale) Figure 2. Pin Configuration Type Function G Digital Ground. G Analog Ground. ...
Page 11
... V 28.63636 MHz clock oscillator source to clock the ADV7401. O This pin should be connected to the 28.63636 MHz crystal or left connect if an external 3.3 V 28.63636 MHz clock oscillator source is used to clock the ADV7401. In crystal mode, the crystal must be a fundamental crystal. O The recommend external loop filter must be connected to this ELPF pin. ...
Page 12
... ADV7401 TIMING DIAGRAMS SDA1/SDA2 SCLK1/SCLK2 P22–P29, VS, HS, LLC1 P2–P9, P12–P19, P22–P29 DCLK_IN HS_IN CONTROL VS_IN INPUTS DE_IN P0–P1, P10–P11, P20–P21, P22–P29, P31–P32, P33–P40 Figure Timing ...
Page 13
... Copy generation management system (CGMS) Gemstar™ 1×/2× electronic program guide compatible • Clocked from a single 28.63636 MHz crystal • Subcarrier frequency lock (SFL) output for downstream video encoder • Differential gain typically 0.5% • Differential phase typically 0.5° Rev. SpA | Page ADV7401 ...
Page 14
... RGB GRAPHICS PROCESSING • 140 MSPS conversion rate supports RGB input resolutions up to 1280 × 1024 @ 75 Hz (SXGA); (110 MSPS conversion rate for ADV7401BSTZ-110); (80 MSPS conversion rate for ADV7401BSTZ-80) • Automatic or manual clamp and gain controls for graphics modes • ...
Page 15
... CP are 525i, 625i, 525p, 625p, 720p 1080i, 1250i, VGA up to SXGA @ 75 Hz (ADV7401KSTZ-140 only), and many other standards not listed here. The CP section of the ADV7401 contains an AGC block. When no embedded sync is present, the video gain can be set manually ...
Page 16
... In SDR mode, a 16-bit 4:2:2 or 24-bit 4:4:4 output is possible. In these modes HS, VS, and FIELD/DE (where applicable) timing refer- ence signals are provided. In DDR mode, the ADV7401 can be configured in an 8-bit 4:2:2 YCrCb or 12-bit 4:4:4 RGB/ YCrCb pixel output interface with corresponding timing signals. ...
Page 17
... CrCb[7:0] OUT - Cb[7:0] OUT - - - - - - - - D11 D10 CHB/C[7:0] (for example, Cr/Cb[7:0]) OUT - CHB[7:0] (for example, B[7:0]) OUT CHB/C[7:0] (for example, Cr/Cb[7:0]) OUT - CHB/C[7:0] (for example, Cr/Cb[7:0]) OUT Cr[7:0] OUT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CHC[7:0] (for example, R[7:0]) OUT B[7:0] IN CHB/C[7:0] IN ADV7401 R[1: R[3: ...
Page 18
... ADV7401 RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS The external loop filter components for the ELPF pin should be placed as close as possible to the respective pins. Figure 8 shows the recommended component values. PIN 46–ELPF 1.69kΩ 10nF 82nF PVDD = 1.8V Figure 8. ELPF Components Rev. SpA | Page ...
Page 19
... TYPICAL CONNECTION DIAGRAM Ω 56 Ω 75 Ω 75 Ω 75 Ω 75 Ω 75 Ω 75 Ω 75 Ω 75 Ω 75 DVDDIO 18 DVDDIO 6 DVDD 90 DVDD 39 DVDD 12 AVDD 63 PVDD 48 PVDD 47 Ω 2.7k Ω 2.7k Figure 9. ADV7401 Rev. SpA | Page ADV7401 DVSS 89 DVSS 40 DVSS 11 DVSSIO 17 DVSSIO 5 PVSS 50 PVSS 49 AVSS 60 AVSS 66 TEST0 70 ...
Page 20
... The ADV7401 is a Pb-free, environmentally friendly product manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and is able to withstand surface-mount soldering 255°C (±5°C). In addition backward compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with SnPb solder pastes at conventional reflow temperatures of 220° ...