adv7401 Analog Devices, Inc., adv7401 Datasheet - Page 11

• Manufacturer Part Number: adv7401
• Description: 10-bit, Integrated, Multiformat Sdtv/hdtv Video Decoder And Rgb Graphics Digitizer
• Manufacturer: Analog Devices, Inc.

Pin No.
4
99
98
81, 19
82, 16
80
78
36
38
37
46
70
59
15
64
65
61, 62
68, 69
67
86
85
79
35
52
77
Mnemonic
HS/CS
VS
FIELD/DE
SDA1, SDA2
SCLK1, SCLK2
ALSB
RESET
LLC1
XTAL
XTAL1
ELPF
TEST0
TEST1
SFL/SYNC_OUT
REFOUT
CML
CAPY1, CAPY2
CAPC1, CAPC2
BIAS
HS_IN/CS_IN
VS_IN
DE_IN
DCLK_IN
SOG
SOY
Type
O
O
O
I/O
I
I
I
O
I
O
O
NC
O
O
O
O
I
I
O
I
I
I
I
I
I
Rev. SpA | Page 11 of 20
HS is a Horizontal Synchronization Output Signal (SDP and CP modes).
CS is a Digital Composite Synchronization Signal (and can be selected
while in CP mode).
Vertical Synchronization Output Signal (SDP and CP modes).
Field Synchronization Output Signal (all interlaced video modes). This
pin also can be enabled as a Data Enable signal (DE) in CP mode to allow
direct connection to a HDMI/DVI Tx IC.
I
control port and SDA2 is the data line for the VBI readback port.
I
line for the control port and SCLK2 is the clock line for the VBI data
readback port.
This pin selects the I
readback ports. ALSB set to Logic 0 sets the address for a write to control
port of 0x40 and the readback address for the VBI port of 0x21. ALSB set
to a logic high sets the address for a write to control port of 0x42 and the
readback address for the VBI port of 0x23.
System Reset Input, Active Low. A minimum low reset pulse width of 5
ms is required to reset the ADV7401 circuitry.
LLC1 is a line-locked output clock for the pixel data (range is 12.825 MHz
to 140 MHz for ADV7401KSTZ-140; 12.825 MHz to 110 MHz for
ADV7401BSTZ-110; 12.825 MHz to 80 MHz for ADV7401BSTZ-80).
Input pin for 28.63636 MHz crystal, or can be overdriven by an external
3.3 V 28.63636 MHz clock oscillator source to clock the ADV7401.
This pin should be connected to the 28.63636 MHz crystal or left as a no
connect if an external 3.3 V 28.63636 MHz clock oscillator source is used
to clock the ADV7401. In crystal mode, the crystal must be a
fundamental crystal.
The recommend external loop filter must be connected to this ELPF pin.
This pin should be left unconnected or alternatively tied to AGND.
This pin should be left unconnected.
Subcarrier Frequency Lock (SFL). This pin contains a serial output stream
which can be used to lock the subcarrier frequency when this decoder is
connected to any Analog Devices digital video encoder. SYNC_OUT is
the sliced sync output signal available only in CP mode.
Internal Voltage Reference Output.
Common-Mode Level Pin (CML) for the internal ADCs.
ADC Capacitor Network.
ADC Capacitor Network.
External Bias Setting Pin. Connect the recommended resistor (1.35 kΩ)
between pin and ground.
Can be configured in CP mode to be either a digital HS input signal or a
digital CS input signal used to extract timing in a 5-wire or 4-wire RGB
mode.
VS Input Signal. Used in CP mode for 5-wire timing mode.
Data Enable Input Signal. Used in 24-bit digital input port mode (for
example, processing 24-bit RGB data from a DVI Rx IC).
Clock Input Signal. Used in 24-bit digital input mode (for example,
processing 24-bit RGB data from a DVI Rx IC) and also in digital CVBS
input mode.
Sync on Green Input. Used in embedded sync mode.
Sync on Luma Input. Used in embedded sync mode.
Function
2
2
C Port Serial Data Input/Output Pins. SDA1 is the data line for the
C Port Serial Clock Input (max clock rate of 400 kHz). SCLK1 is the clock
2
C address for the ADV7401 control and VBI
ADV7401