z893232yfsc ZiLOG Semiconductor, z893232yfsc Datasheet - Page 23

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z893232yfsc

Manufacturer Part Number
z893232yfsc
Description
16-bit Digital Signal Processors
Manufacturer
ZiLOG Semiconductor
Datasheet
TIMER/COUNTERS
The Z89323/373/393 has two 16-bit Timer/Counters that
can be independently configured to operate in various
modes. Each is implemented as a 16-bit Load Register
(TMLR) and a 16-bit down counter (TMR). Timer/Counter
inputs can be selected from among UI0 or UI1 pins and
outputs from among UO0 or UO1 pins. The Timer/Counter
clock is a scaled version of system clock. Each counter has
an 8-bit clock prescaler with divide count controlled by the
16-bit Prescaler Load Register (TPLR). The clock rates of
the two timer/counters are independent of each other.
External input events occur optionally on the rising edge,
DS95DSP0101 Q4/95
Test
15
14
13 12 11
MODE
P R E L I M I N A R Y
Figure 14. TCTL Register
8
OUT
INV
7
6
OUT
SEL
the falling edge, or both rising and falling edges of the
input. Output actions on external pins can be programmed
to occur with either polarity. The Timer/Counter operational
modes are selected through the 16-bit Control Register
(TCTL). This register defines the operational modes of its
companion Timer (Figure 14).
Each Timer contains a set of five 16-bit Registers. The Ext
Register Assignment specifies the location of each Timer
Registers. All accesses to Timer Registers occur with zero
Wait States.
5
4
EVENT
INP
3
2
SEL
INP
1
CE
0
Count Enable
Input Select
Input Event
Output Select
Output Invert
Timer Mode
Reserved
Test Mode
16-B
IT
D
IGITAL
S
IGNAL
Z89323/373/393
P
ROCESSORS
23

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