z893232yfsc ZiLOG Semiconductor, z893232yfsc Datasheet - Page 34

• Manufacturer Part Number: z893232yfsc
• Description: 16-bit Digital Signal Processors
• Manufacturer: ZiLOG Semiconductor

CLOCK Circuits
The clock generator includes Phase-Locked Loop (PLL)
circuit to enable use of low frequency crystal. The benefits
of using low frequency crystal are low system cost, low
power consumption and low EMI. The PLL circuit can be
bypass (s/w controlled).
The clock generated by the PLL circuit (VCO clock) is
programmable and controlled by the PLL Divider register.
Notes:
*
* * Default (power-up) mode of operation.
34
STOP_OSC
In this clock mode, it is possible to use external clock source instead
of the internal oscillator source.
32 kHz
0
0
0
0
1
1
STOP_VCO
Off-Chip
0
0
1
1
1
1
Detector
Phase
LPF
On-Chip
:2
STOP_OSC
Figure 26. PLL Functional Block Diagram
BYPASS_PLL
P R E L I M I N A R Y
Divider
Table 12. CLOCK Modes
8-Bit
VCO
0
1
0
1
0
1
STOP_VCO
PLL Divider
Bank4 / Ext5
DSP (System) clock source is programmable and can be
one of the 4 options: VCO clock, VCO clock divided by 2,
VCO clock divided by 4 or twice the crystal frequency.
Whenever the PLL circuit is switched from Stop VCO to
Enable VCO, a software delay of 10 msec must be used
before switching the system clock from the oscillator to the
PLL, in order to give the PLL time to be stable.
Mode
0) Normal - High frequency clock
1) 32 Khz - VCO running (fast switching time)**
2) STOP CLOCK - Oscillator running
3) 32 Khz
4) STOP CLOCK
5) EXTERNAL CLOCK source *
Clock Source
:2
:2
00
01
10
11
BYPASS_PLL
MUX
16-B
0
1
DS95DSP0101 Q4/95
IT
D
MUX
IGITAL
S
IGNAL
Z89323/373/393
System
Clock
P
ROCESSORS