mc68hc908jb8 Freescale Semiconductor, Inc, mc68hc908jb8 Datasheet - Page 167

• Manufacturer Part Number: mc68hc908jb8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
If V
(Table 10-1
clock, f
mode entry
by-two of the external clock. Holding the PTA3 pin low when entering
monitor mode causes a bypass of a divide-by-two stage at the oscillator
only if V
is equal to the OSCXCLK frequency.
Entering monitor mode with V
long as V
8. System Integration Module (SIM)
operation.)
If entering monitor mode without high voltage on IRQ and reset vector
being blank ($FFFE and $FFFF)
applied voltage is V
including the PTA3 frequency divisor selection, are not in effect. This is
to reduce circuit requirements when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is
always disabled regardless of the state of IRQ or the RST.
Figure
the reset vector is blank and IRQ = V
required for a baud rate of 9600.
DD
+V
XCLK
10-2. shows a simplified diagram of the monitor mode entry when
DD
DD
HI
+V
is applied to IRQ and PTA3 is low upon monitor mode entry
. If PTA3 is high with V
(Table 10-1
condition set 1), the bus frequency is a equal to the external
+ V
HI
Monitor ROM (MON)
HI
is applied to IRQ. In this event, the OSCOUT frequency
is applied to either the IRQ or the RST. (See
DD
), then all port A pin requirements and conditions,
condition set 2), the bus frequency is a divide-
DD
(Table 10-1
+ V
DD
HI
DD
+V
for more information on modes of
on IRQ, the COP is disabled as
. An external clock of 6MHz is
HI
applied to IRQ upon monitor
condition set 3, where IRQ
Functional Description
Monitor ROM (MON)
Technical Data
Section
167