mpc8360e Freescale Semiconductor, Inc, mpc8360e Datasheet - Page 16

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mpc8360e

Manufacturer Part Number
mpc8360e
Description
Mpc8360e Powerquicc Ii Pro Family
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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RESET Initialization
4.1
Table 7
4.2
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode.
(CLKIN/PCI_CLK) AC timing specifications for the device.
5
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8360E/58E.
16
Input high voltage
Input low voltage
CLKIN input current
PCI_SYNC_IN input current
PCI_SYNC_IN input current
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
CLKIN/PCI_CLK frequency
CLKIN/PCI_CLK cycle time
CLKIN/PCI_CLK rise and fall time
CLKIN/PCI_CLK duty cycle
CLKIN/PCI_CLK jitter
Notes:
1. Caution: The system, core, USB, security, and 10/100/1000 Ethernet must not exceed their respective maximum or
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set
minimum operating frequencies.
low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
RESET Initialization
provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the device.
Parameter
DC Electrical Characteristics
AC Electrical Characteristics
Parameter/Condition
OV
0.5 V ≤ V
Table 7. CLKIN DC Electrical Characteristics
Table 8. CLKIN AC Timing Specifications
DD
0 V ≤ V
0 V ≤ V
– 0.5V ≤ V
Condition
IN
IN
≤ OV
IN
≤ 0.5V or
≤ OV
t
DD
KHK
IN
Symbol
t
f
t
KH
≤ OV
CLKIN
CLKIN
DD
– 0.5 V
/t
, t
CLKIN
KL
DD
Min
0.6
Symbol
15
40
V
V
I
I
I
IN
IN
IN
IH
IL
Table 8
Typical
1.0
–0.3
provides the clock input
Min
2.7
66.67
±150
Max
2.3
60
OV
Freescale Semiconductor
DD
±100
MHz
Unit
Max
±10
±10
0.4
ns
ns
ps
%
+ 0.3
Notes
4, 5
1
2
3
Unit
μA
μA
μA
V
V

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