mpc8360e Freescale Semiconductor, Inc, mpc8360e Datasheet - Page 25

• Manufacturer Part Number: mpc8360e
• Description: Mpc8360e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

Figure 8
Table 22
signals of the DDR controller for various loadings, which can be useful for a system utilizing the DLL.
These numbers are the result of simulations for one topology. The delay numbers will strongly depend on
the topology used. These delay numbers show the total delay for the address and command to arrive at the
DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the
system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup
requirements at the DRAM.
Freescale Semiconductor
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
ADDR/CMD
shows the DDR SDRAM output timing diagram for source synchronous mode.
MDQS[n]
provides approximate delay information that can be expected for the address and command
MDQ[x]
MCK[n]
MCK[n]
Figure 8. DDR SDRAM Output Timing Diagram for Source Synchronous Mode
4 devices (12 pF)
9 devices (27 pF)
36 devices (108 pF) + 40 pF compensation capacitor
36 devices (108 pF) + 80 pF compensation capacitor
Table 22. Expected Delays for Address/Command
Write A0
t
DDKHMP
t
t
DDKHDX
DDKHAS
Load
t
MCK
,t
NOOP
DDKHCS
t
t
D0
DDKHAX
DDKHMH
t
DDKHDS
,t
DDKHCX
D1
t
DDKLDS
t
DDKLDX
Delay
3.0
3.6
5.0
5.2
Unit
ns
ns
ns
ns
DDR and DDR2 SDRAM
t
DDKHME
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