mpc8640 Freescale Semiconductor, Inc, mpc8640 Datasheet - Page 47

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mpc8640

Manufacturer Part Number
mpc8640
Description
Integrated Host Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Figure 27
Freescale Semiconductor
LA[27:31]/LBCTL/LBCKE/LOE/
Internal launch/capture clock
LSDA10/LSDWE/LSDRAS/
Output (Address) Signal:
LSDCAS/LSDDQM[0:3]
Output (Data) Signals:
shows the local bus signals in PLL bypass mode.
LAD[0:31]/LDP[0:3]
LAD[0:31]/LDP[0:3]
Output Signals:
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Input Signals:
In PLL bypass mode, LCLK[n] is the inverted version of the internal clock
with the delay of
of the internal clock and are captured at falling edge of the internal clock,
with the exception of the LGTA/LUPWAIT signal, which is captured at the
rising edge of the internal clock.
Input Signal:
LUPWAIT
LAD[0:31]
LCLK[n]
LGTA
LALE
Figure 27. Local Bus Signals (PLL Bypass Mode)
t
LBKHKT.
In this mode, signals are launched at the rising edge
t
LBKLOV1
t
LBKLOV2
NOTE
t
t
LBKLOV3
LBKLOV4
t
LBKHKT
t
LBIVKH1
t
LBOTOT
t
t
LBKLOX1
LBKLOX2
t
LBIXKH1
t
LBIVKL2
t
LBIXKL2
Local Bus
t
t
LBKLOZ1
LBKLOZ2
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