mpc8640 Freescale Semiconductor, Inc, mpc8640 Datasheet - Page 62

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mpc8640

Manufacturer Part Number
mpc8640
Description
Integrated Host Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
High-Speed Serial Interfaces (HSSI)
13.2.3
The following list explains characteristics of interfacing with other differential signaling levels.
62
SD n _REF_CLK
SD n _REF_CLK
With on-chip termination to SGND, the differential reference clocks inputs are HCSL (high-speed
current steering logic) compatible DC-coupled.
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can
be used but may need to be AC-coupled due to the limited common mode input range allowed (100
to 400 mV) for DC-coupled connection.
LVPECL outputs can produce signal with too large amplitude. It may need to be DC-biased at
clock driver output first and followed with series attenuation resistor to reduce the amplitude, in
addition to AC-coupling.
Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Interfacing With Other Differential Signaling Levels
SD n _REF_CLK
SD n _REF_CLK
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Figure 42. Single-Ended Reference Clock Input DC Requirements
200mV < Input Amplitude or Differential Peak < 800mV
400 mV < SD n _REF_CLK Input Amplitude < 800 mV
Vmin > Vcm – 400 mV
Vmax < Vcm + 400 mV
0 V
Freescale Semiconductor
Vcm

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