dp83840a National Semiconductor Corporation, dp83840a Datasheet - Page 22

• Manufacturer Part Number: dp83840a
• Description: 10/100 Mb/s Ethernet Physical Layer
• Manufacturer: National Semiconductor Corporation

Version A
3.0 Functional Description
of the current state of synchronization and reset in order to
re-acquire synchronization.
The value of the time-out for this timer may be modified from
722 s to 2 ms b y setting bit 14 of the PCR (address 17h) to
one. The 2 ms option allows applications with Maximum
Transmission Units (packet sizes) larger than IEEE 802.3 to
maintain descrambler synchronization (i.e. Token Ring/
Fast-Ethernet switch/router applications).
Additionally, this timer may be disabled entirely by setting
bit 13 of the PCR (address 17h) to one. The disabling of the
time-out timer is not recommended as this will eventually
result in a lack of synchronization between the transmit
scrambler and the receive descrambler which will corrupt
data.
3.4.4 Code-group Alignment
The code-group alignment module operates on unaligned
5-bit data from the descrambler (or, if the descrambler is
bypassed, directly from the NRZI/NRZ decoder) and
converts it into 5B code-group data (5 bits). code-group
alignment occurs after the J/K code-group pair is detected.
Once the J/K code-group pair (11000 10001) is detected,
subsequent data is aligned on a fixed boundary.
3.4.5 Code-group Decoder
The code-group decoder functions as a look up table that
translates incoming 5B code-groups into 4B nibbles. The
code-group decoder first detects the J/K code-group pair
preceded by IDLE code-groups and replaces the J/K with
MAC preamble. Specifically, the J/K 10-bit code-group pair
is replaced by the nibble pair (0101 0101). All subsequent
5B code-groups are converted to the corresponding 4B
nibbles for the duration of the entire packet. This
conversion ceases upon the detection of the T/R code-
group pair denoting the End of Stream Delimiter (ESD) or
with the reception of a minimum of two IDLE code-groups.
3.4.6 Collision Detect
Half Duplex collision detection for 100 Mb/s follows the
model of 10BASE-T (refer to section 3.7.3). Collision
detection is indicated by the COL pin of the MII whenever
both the transmit and receive functions within the
DP83840A attempt to process packet data simultaneously.
For Full Duplex applications the COL signal is never
asserted.
3.4.7 Carrier Sense
Carrier Sense (CRS) is asserted, as a function of receive
activity, upon the detection of two non-contiguous zeros
occurring within any 10-bit boundary of the receive data
stream. CRS is asserted, as a function of transmit activity
(depending on the mode of operation), whenever the
TX_EN (transmit enable) input to the DP83840A is
asserted.
For 100 Mb/s Half Duplex operation (non-repeater mode),
CRS is asserted during either packet transmission or
reception.
In REPEATER mode (pin 47/bit 12, register address 17h),
CRS is only asserted due to receive activity.
For 100 Mb/s Full Duplex operation, the behavior of CRS
depends on bit 6 of the LBREMR (address 18h). If this bit
is zero, then CRS is asserted only due to receive activity. If
this bit is one, then CRS is asserted only due to transmit
(Continued)
22
activity. This operation allows flexibility for interfacing a Full
Duplex MAC to the DP83840A.
When the IDLE code-group pair is detected in the receive
data stream, CRS is deasserted. In modes where transmit
activity results in the assertion of CRS, the deassertion of
TX_EN results in the immediate deassertion of CRS.
The carrier sense function is independent of code-group
alignment.
3.4.8 100 Mb/s Receive State Machine
The DP83840A implements the 100BASE-X receive state
machine diagram as given in ANSI/IEEE Standard 802.3u/
D5, Clause 24.
3.4.9 100BASE-X Link Integrity Monitor
The 100BASE-X Link Integrity Monitor function (LIM)
allows the receiver to ensure that reliable data is being
received. Without reliable data reception, the LIM will halt
both transmit and receive operations until such time that a
valid link is detected (i.e. good link.)
If Auto-Negotiation is not enabled, then a valid link will be
indicated once SD+/- is asserted continuously for 500 s.
If Auto-Negotiation is enabled, then Auto-Negotiation will
further qualify a valid link as follows:
A valid link may be detected externally by either the LED3
output or by reading bit 2 of the Basic Mode Status
Register (address 01h.)
3.4.10 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is an error
condition that occurs in the 100BASE-X receiver if carrier is
detected (CRS asserted) and a valid /J/K/ set of code
groups (SSD) is not received.
If this condition is detected, then the DP83840A will assert
RX_ER and present RXD[3:0] = 1110 to the MII for the
cycles that correspond to received 5B code-groups until at
least two IDLE code groups are detected. In addition, the
False Carrier Event Counter (address 12h) and the RX_ER
Counter (address 15h) will be incremented by one.
Once at least two IDLE code groups are detected, RX_ER
and CRS become de-asserted.
RX_ER becomes RXD[4] in transparent mode (Bypass_
4B5B), such that RXD[4:0]=11110 during a Bad SSD
event.
When bit 12 of the LBREMR is one (Bypass Align mode),
RXD[3:0] and RX_ER/RXD[4] are not modified regardless
of the state of bit 15 of the LBREMR (Bad SSD Enable.)
Disabling the Bad SSD function supports non-IEEE 802.3u
compliant applications.
3.4.11 Far End Fault Indication
Auto-Negotiation provides a mechanism for transferring
information from the Local Station to the Link Partner that a
remote fault has occurred for 100BASE-TX. As Auto-
Negotiation is not currently specified for operation over
fiber, the Far End Fault Indication function (FEFI) provides
this capability for 100BASE-FX applications.
The descrambler must receive a minimum of 15 IDLE
code groups for proper link initialization
Auto-Negotiation must determine that the 100BASE-X
function should be enabled.
National Semiconductor