dp83840a National Semiconductor Corporation, dp83840a Datasheet - Page 27

• Manufacturer Part Number: dp83840a
• Description: 10/100 Mb/s Ethernet Physical Layer
• Manufacturer: National Semiconductor Corporation

Version A
3.0 Functional Description
3.5.5.2 Repeater Clock Distribution Example
The clock distribution within a multi-port repeater can be
designed in a variety of ways. Figure 12 provides a
simplified example of one possible timing distribution
scheme in a 100 Mb/s only repeater design. It should be
noted that in order to support Auto-Negotiation, a 20 MHz
reference would be required for each DP83840A device.
BUFFER
MHz
25
DP83840A (1)
FIGURE 12. Typical 100 Mb/s Repeater Clock Interconnection
DP83223
(1)
FIGURE 11. Typical Adapter Clock and Data Typical
MAC
(Continued)
25 MHz
RX_CLK
TX_CLK
DP83840A (2)
RXD
TXD
DP83223
27
(2)
PHY
MHz
(DP83850
50
100RIC)
ENDEC
Due to the demanding timing constraints required to
maintain standards compliance, great care must be
taken in the design and layout of a multi-port repeater
system. The example provided in Figure 12 illustrates
interconnection only and should not be considered as a
reference design.
RX_CLK
TD
RD
National Semiconductor
PMD
DP83840A (12)
DP83223
(12)