palce20ra10 Lattice Semiconductor Corp., palce20ra10 Datasheet - Page 12

• Manufacturer Part Number: palce20ra10
• Description: 24-pin Asynchronous Ee Cmos Programmable Array Logic
• Manufacturer: Lattice Semiconductor Corp.

ENDURANCE CHARACTERISTICS
The PALCE20RA10 is manufactured using our ad-
vanced Electrically Erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
Robustness
The PALCE20RA10 has been designed with some
unique features that make it extremely robust, even
when operating in high-speed design environments.
Pull-up resistors on the inputs and I/Os cause uncon-
nected pins to default to the HIGH state. Please note
that these pull-up resistors are only for this purpose, and
do not provide enough current to sufficiently pull a bus
line high. We recommend that external pull-up or
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Symbol
t
DR
N
Parameter
Min Pattern Data Retention Time
Min Reprogramming Cycles
Protection
Clamping
ESD
and
> 50 k
V
CC
Programming
Pins Only
PALCE20RA10 Family
Provides ESD
Protection and
Clamping
V
Test Conditions
Max Storage Temperature
Max Operating Temperature
Normal Programming Conditions
CC
Typical Output
Typical Input
V
parts. As a result, the device can be erased and
reprogrammed—a feature which allows 100% testing at
the factory.
pull-down resistors be used if the condition of a floating
bus line exists.
Input-clamping circuitry limits negative overshoot, elimi-
nating the possibility of false clocking caused by subse-
quent ringing. A special noise filter makes the
programming circuitry completely insensitive to any
positive overshoot that has a pulse width of less than
about 100 ns.
CC
Programming
Detection
Voltage
> 50 k
Circuitry
V
Preload
CC
Overshoot
Positive
Filter
Feedback
Input
Min
100
10
20
Programming
Circuitry
15434H-17
Cycles
Years
Years
Unit
2-195