palce20ra10 Lattice Semiconductor Corp., palce20ra10 Datasheet - Page 5

• Manufacturer Part Number: palce20ra10
• Description: 24-pin Asynchronous Ee Cmos Programmable Array Logic
• Manufacturer: Lattice Semiconductor Corp.

Three-State Outputs
The devices provide a product term dedicated to local
output control. There is also a global output control pin.
The output is enabled if both the global output control
pin is LOW and the local output control product term is
HIGH. If the global output control pin is HIGH, all outputs
will be disabled. If the local output control product term is
LOW, then that output will be disabled.
Security Bit
A security bit is also provided to prevent unauthorized
copying of PAL device patterns. Once the bit is pro-
grammed, the circuitry enabling verification is perma-
nently disabled, and the array will read as if every bit is
programmed. With verification not operating, it is impos-
sible to simply copy the PAL device pattern on a PAL de-
vice programmer. The security bit can only be erased in
conjunction with the entire pattern.
Programmable Polarity
The outputs can be programmed either active-LOW or
active-HIGH. This is represented by the Exclusive-OR
gate shown in the PALCE20RA10 logic diagram. When
the output polarity bit is programmed, the lower input to
the Exclusive-OR gate is HIGH, so the output is active-
HIGH. Similarly when the output polarity bit is
unprogrammed, the output is active-LOW. The pro-
grammable output polarity feature allows the user a
higher degree of flexibility when writing equations.
Programming and Erasing
The PALCE20RA10 can be programmed on standard
logic programmers. Approved programmers are listed
at the end of this databook. It also may be erased to re-
set a previously configured device back to its virgin
state. Erasure is automatically performed by the pro-
gramming hardware. No special erase operation is re-
quired.
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PALCE20RA10 Family
Output Register Preload
The output registers on the PALCE20RA10 can be
preloaded from the output pins to facilitate functional
testing of complex state machine designs. This feature
allows direct loading of arbitrary states, making it unnec-
essary to cycle through long test vector sequences to
reach a desired state. In addition, transitions from illegal
states can be verified by loading illegal states and ob-
serving proper recovery. Register preload is controlled
by a TTL-level signal, making it a convenient board-level
initialization function. Details on output register preload
can be found on page 16.
Power-Up Reset
All flip-flops power up to a logic LOW for predictable
system initialization. Registered outputs of the
PALCE20RA10 will be HIGH due to the output inverter.
The state of combinatorial outputs will be a function of
the logic. Details on power-up reset can be found on
page 16.
Quality and Testability
The PALCE20RA10 offers a very high level of built-in
quality. The erasability of the device provides a means
of verifying performance of all AC and DC parameters.
In addition, this verifies complete programmability and
functionality of the device to provide the highest pro-
gramming yields and post-programming functional
yields in the industry.
Technology
The high-speed PALCE20RA10 is fabricated with
Our advanced electrically erasable (EE) CMOS proc-
ess. The array connections are formed with proven EE
cells. Inputs and outputs are designed to be compatible
with TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.