enc28j60 Microchip Technology Inc., enc28j60 Datasheet - Page 7

• Manufacturer Part Number: enc28j60
• Description: Stand-alone Ethernet Controller With Spi Interface
• Manufacturer: Microchip Technology Inc.

2.0
2.1
The ENC28J60 is designed to operate at 25 MHz with
a crystal connected to the OSC1 and OSC2 pins. The
ENC28J60 design requires the use of a parallel cut
crystal. Use of a series cut crystal may give a frequency
out of the crystal manufacturer specifications. A typical
oscillator circuit is shown in Figure 2-1.
The ENC28J60 may also be driven by an external clock
source connected to the OSC1 pin as shown in
Figure 2-2.
FIGURE 2-1:
FIGURE 2-2:
© 2006 Microchip Technology Inc.
Note 1: A series resistor, R
External System
3.3V Clock from
Note 1: Duty cycle restrictions must be observed.
C
C
2: The feedback resistor, R
2: A resistor to ground may be used to reduce
EXTERNAL CONNECTIONS
Oscillator
1
2
Open
strip cut crystals.
range of 2 to 10 M .
system noise. This may increase system
current.
XTAL
R
(2)
S
(1)
OSC2
OSC1
CRYSTAL OSCILLATOR
OPERATION
EXTERNAL CLOCK
SOURCE
R
F
S
(2)
, may be required for AT
(1)
ENC28J60
F
OSC1
OSC2
, is typically in the
To Internal Logic
ENC28J60
Preliminary
2.2
The ENC28J60 contains an Oscillator Start-up Timer
(OST) to ensure that the oscillator and integrated PHY
have stabilized before use. The OST does not expire
until 7500 OSC1 clock cycles (300 s) pass after
Power-on Reset or wake-up from Power-Down mode
occurs. During the delay, all Ethernet registers and
buffer memory may still be read and written to through
the SPI bus. However, software should not attempt to
transmit any packets (set ECON1.TXRTS), enable
reception of packets (set ECON1.RXEN) or access any
MAC, MII or PHY registers during this period.
When the OST expires, the CLKRDY bit in the ESTAT
register will be set. The application software should poll
this bit as necessary to determine when normal device
operation can begin.
Note:
Oscillator Start-up Timer
After a Power-on Reset, or the ENC28J60
is removed from Power-Down mode, the
CLKRDY bit must be polled before
transmitting packets, enabling packet
reception or accessing any MAC, MII or
PHY registers.
ENC28J60
DS39662B-page 5