isp1582 NXP Semiconductors, isp1582 Datasheet - Page 17

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isp1582

Manufacturer Part Number
isp1582
Description
Hi-speed Universal Serial Bus Peripheral Controller
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
ISP1582_6
Product data sheet
7.16 Power supply
The RESET_N pin can either be connected to V
externally controlled (by the microcontroller, ASIC, and so on). When V
connected to the RESET_N pin, the internal pulse width t
The power-on reset function can be explained by viewing the dips at t2 to t3 and t4 to t5
on the V
t0 — The internal POR starts with a HIGH level.
t1 — The detector will see the passing of the trip level and a delay element will add
another t
t2-t3 — The internal POR pulse will be generated whenever V
more than 11 s.
t4-t5 — The dip is too short (< 11 s) and the internal POR pulse will not react and will
remain LOW.
Figure 9
The ISP1582 can be powered by 3.3 V
details, see
If the ISP1582 is powered by V
provides a 1.8 V supply voltage for the internal logic.
Fig 8. POR timing
Fig 9. Clock with respect to the external POR
t0
CC(POR)
(1) PORP = Power-On Reset Pulse.
Power on V
Stable external clock is to be available at B.
The ISP1582 is operational at C.
PORP
shows the availability of the clock with respect to the external POR.
Figure
t1
RESET_N
before it drops to LOW.
t
PORP
external
curve
clock
V
CC
CC
10.
at A.
Rev. 06 — 20 September 2007
(Figure
8).
A
CC
= 3.3 V, an integrated 3.3 V-to-1.8 V voltage regulator
500 s
t2
0.3 V, and 3.3 V at the interface. For connection
B
2 ms
t3
CC
t
PORP
Hi-Speed USB Peripheral Controller
(using the internal POR circuit) or
PORP
t4
C
CC(POR)
will typically be 200 ns.
t5
004aaa927
drops below V
CC
© NXP B.V. 2007. All rights reserved.
ISP1582
is directly
004aaa389
PORP
V
V
BAT(POR)
trip
(1)
17 of 69
trip
for

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