mc33996ek/r2 Freescale Semiconductor, Inc, mc33996ek/r2 Datasheet - Page 7

• Manufacturer Part Number: mc33996ek/r2
• Description: 16-output Switch With Spi Control
• Manufacturer: Freescale Semiconductor, Inc

Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS
noted. Where applicable, typical values reflect the parameter’s approximate average value with V
POWER OUTPUT TIMING (VPWR)
DIGITAL INTERFACE TIMING (CS, SO, SI, SCLK)
Notes
Output Slew Rate
Output Turn ON Delay Time
Output Turn OFF Delay Time
Output ON Short Fault Disable Report Delay
Output OFF Open Fault Delay Time
Output PWM Frequency
Required Low State Duration on V
Falling Edge of
Falling Edge of SCLK to Rising Edge of CS
SI to Falling Edge of SCLK
Falling Edge of SCLK to SI
SI,
SI,
Time from Falling Edge of
Time from Rising Edge of
Time from Rising Edge of SCLK to SO Data Valid
15.
16.
17.
18.
19.
20.
21.
22.
23.
Characteristics noted under conditions of 3.1 V ≤ SO
R
V
Required Setup Time
Required Setup Time
Required Setup Time
Required Hold Time
CS
CS
PWR
L
= 60Ω
, SCLK Signal Rise Time
, SCLK Signal Fall Time
Output slew rate measured across a 60 Ω resistive load.
Output turn ON and OFF delay time measured from 50% rising edge of
Duration of fault before fault bit is set. Duration between access times must be greater than 450 µs to read faults.
This parameter is guaranteed by design; however, it is not production tested.
Rise and Fall time of incoming SI,
Time required for valid output status data to be available on SO pin.
Time required for output states data to be terminated at SO pin.
Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
This parameter is guaranteed by design. Production test equipment used 4.16 MHz, 5.5 V/3.1 V SPI Interface.
≤ 0.2 V
(15)
CS
(18)
to Rising Edge of SCLK
CS
CS
(16)
to SO High Impedance
(16)
to SO Low Impedance
(19)
Characteristic
(19)
PWR
(17)
for Reset
DYNAMIC ELECTRICAL CHARACTERISTICS
CS
, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
(17)
(22)
(23)
(20)
(21)
PWR
≤ 5.5 V, 5.0 V ≤ V
CS
to 80% and 20% of initial voltage.
t
t
DLY
DLY
Symbol
t
t
t
t
t
DLY
DLY
t
t
t
SI
SO
t
SO
t
t
FREQ
t
VALID
t
LEAD
SI
R
SR
F
RST
LAG
PWR
(
(short)
(open)
hold
(SI)
(
(SI)
(
(
su
(on)
(off)
dis
en
)
)
)
)
≤ 18 V, -40°C ≤ T
DYNAMIC ELECTRICAL CHARACTERISTICS
Min
100
100
100
1.0
1.0
1.0
50
16
20
–
–
–
–
–
–
–
ELECTRICAL CHARACTERISTICS
PWR
A
= 13 V, T
≤ 125°C unless otherwise
Typ
2.0
2.0
4.0
5.0
5.0
25
–
–
–
–
–
–
–
–
–
–
A
= 25°C.
Max
450
450
2.0
10
10
10
10
50
50
80
–
–
–
–
–
–
33996
V/µs
Unit
kHz
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
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