z80230 ZiLOG Semiconductor, z80230 Datasheet - Page 10

• Manufacturer Part Number: z80230
• Description: Esc Enhanced Serial Communication Controller
• Manufacturer: ZiLOG Semiconductor

AC CHARACTERISTICS
Z80230 General Timing Table
No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16a TcRTX
16b TxRX(DPLL)
17
18
19
20
21
22
Notes:
[1] RxC is /RTxC or /TRxC, whichever is supplying the receive clock.
[2] TxC is /TRxC or /RTxC, whichever is supplying the transmit clock.
[3] Both /RTxC and /SYNC have 30 pf capacitors to ground connected to them.
[4] Synchronization of RxC to PCLK is eliminated in divide by four operation.
[5] Parameter applies only to FM encoding/decoding.
[6] Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to case PCLK requirements.
[7] The maximum receive or transmit data rate is 1/4 PCLK.
[8] Applies to DPLL clock source only. Maximum data rate of 1/4 PCLK still applies. DPLL clock should have a 50% duty cycle.
* Units in nanoseconds (ns).
10
Symbol
TdPC(REQ)
TsPC(W)
TsRXC(PC)
TsRXD(RXCr)
ThRXD(RxCr)
TsRXD(RXCf)
ThRXD(RXCf)
TsSY(RXC)
ThSY(RXC)
TsTXC(PC)
TdTXCf(TXD)
TdTxCr(TXD)
TdTXD(TRX)
TwRTXh
TwRTXl
TcRTXX
TwTRXh
TwTRXl
TcTRX
TwEXT
TwSY
Parameter
/PCLK Low to W/REQ Valid
/PCLK Low to Wait Inactive
/RxC High to /PCLK High Setup Time
RxD to /RxC High Setup Time
RxD to /RxC High Hold Time
RxD to /RxC Low Setup Time
RxD to /RxC Low Hold Time
SYNC to /RxC High Setup Time
SYNC to /RxC High Hold Time
/TxC Low to /PCLK High Setup Time
/TxC Low to TxD Delay
/TxC High to TxD Delay
TxD to TRxC Delay
RTxC High Width
TRxC Low Width
RTxC Cycle Time
DPLL Cycle Time Min
Crystal Osc. Period
TRxC High Width
TRxC Low Width
TRxC Cycle Time
DCD or CTS Pulse Width
SYNC Pulse Width
5TcPc
-150
Min
125
125
120
120
400
100
120
120
400
120
120
NA
NA
50
0
0
10 MHz
1000
Max
200
300
150
150
140
5TcPc
-100
244
100
244
Min
NA
NA
60
60
80
80
31
80
80
70
70
0
0
16 MHz
1000
Max
110
180
85
85
80
Notes*
[1,4]
[1]
[1]
[1,5]
[1,5]
[1]
[1]
[2,4]
[2]
[2,5]
[6]
[6]
[6,7]
[7,8]
[3]
[6]
[6]
[6,7]