sta323wqs STMicroelectronics, sta323wqs Datasheet - Page 39

• Manufacturer Part Number: sta323wqs
• Description: 2.1-channel High-efficiency Digital Audio System With Qsound Qhd??
• Manufacturer: STMicroelectronics

STA323WQS
7.3.1
Table 22.
Table 23.
Figure 49. Serial input and data timing
Delay serial clock enable
Table 24.
Table 25.
Each channel received from the I
the channel input mapping registers. This allows processing flexibility. The default settings of
these registers map each I
BICKI frequency (slave mode)
BICKI pulse width high (T1) (slave mode)
BICKI active to LRCKI edge delay (T2)
BICKI active to LRCKI edge delay (T3)
SDI valid to BICKI active setup (T4)
BICKI active to SDI hold time (T5)
5
6
7
g
Bit
Bit
BICKI
R/W
R/W
R/W
R/W
R/W
Supported serial audio input formats (continued)
Serial input data timing characteristics (Fs = 32 to 192 kHz)
Delay serial clock enable
Channel input mapping
LRCKI
BICKI
0
0
1
RST
RST
SDI
SAI (3...0)
Signal
1010
1110
DSCKE
C1IM
C2IM
T2
2
Name
Name
S input channel to its corresponding processing channel.
2
S can be mapped to any internal processing channel via
T4
T3
SAIFB
X
X
0: no serial clock delay
1: serial clock delay by 1 core clock cycle to tolerate
anomalies in some I
0: processing channel 1 receives left I
1: processing channel 1 receives right I
0: processing channel 2 receives left I
1: processing channel 2 receives right I
T5
T0
2
Right-justified 18-bit data
Right-justified 16-bit data
T1
S master devices
Description
Description
Interface format
12.5 MHz max.
Frequency
40 ns min.
20 ns min.
20 ns min.
20 ns min.
20 ns min.
Register descriptions
2
2
S input
S input
2
2
S input
S input
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