hmp8117 Intersil Corporation, hmp8117 Datasheet
hmp8117
Available stocks
Related parts for hmp8117
hmp8117 Summary of contents
Page 1
... Data Sheet NTSC/PAL Video Decoder The HMP8117 is a high quality NTSC and PAL video decoder with internal A/D converters compatible with NTSC M, PAL and combination N (N video standards. Both composite and S-video (Y/C) input formats are supported. A 2-line comb filter plus a user-selectable chrominance trap filter provide high quality Y/C separation ...
Page 2
Functional Block Diagram SEE ANALOG FRONT END BLOCK DIAGRAM EXTERNAL ANTI-ALIAS FILTER Y OUT CVBS1 INPUT CLAMP, MUX, CVBS2 COARSE AGC, DC-RESTORE CVBS3(Y) LCAP EXTERNAL C COARSE AGC ANTI-ALIAS DC-RESTORE FILTER CCAP SEE DIGITAL PROCESSING BLOCK DIAGRAM Y IN YIN[7:0] ...
Page 3
Analog Front End Block Diagram (EXTERNAL) (INTERNAL CLAMP) VAA 1.75V INPUT TO + nmos - 1.0μF VIDEO MUX # 75 PIN 50μA 1.0μF VID1 CVBS1 CLAMP 7 1.0μF VID2 CVBS2 CLAMP 6 1.0μF Y_IN CVBS3(Y) CLAMP ...
Page 4
Digital Processing Block Diagram CLK2 FREQ SELECT (24.54, 27.0 or 29.5MHz) CHROMA CHROMA PLL LOOP PLL NCO FILTER CLK2 TO 4FSC RATIO 4FSC CLOCK CHROMA DATA C[7:0] LINE M DELAY C, CVBS U COMB X FILTER INPUT SAMPLE RATE CONVERTER ...
Page 5
... This section discusses those external aspects of the HMP8117. Analog Video Inputs The HMP8117 supports either three composite or two composite and one S-video input. Three analog video inputs (CVBS 1-3) are used to select which one of three composite video sources are to be decoded ...
Page 6
... The Y/C separation process is responsible for separating the composite video signal into these two components. The HMP8117 utilizes a comb filter to minimize the artifacts that are associated with the Y/C separation process. Input Sample Rate Converter The input sample rate converter is used to convert video data sampled at the CLK2 rate to a virtual 4xf comb filtering and color demodulation ...
Page 7
... PLL and result in pixel decoding errors. Digital Processing of Video Once the luma and chroma have been separated the HMP8117 then performs programmable modifications (i.e. contrast, coring, color space conversions, color AGC, etc.) to the decoded video signal CbCr Conversion ...
Page 8
... The 16-bit R′G′B′ data may be converted to 16-bit linear RGB, using the following equations. Although the PAL specifications specify a gamma of 2.8, a gamma of 2.2 is normally used. The HMP8117 allows the selection of the gamma to be either 2.2 or 2.8, independent of the video standard. 2.2 2.2 2 ...
Page 9
... VIDEO INPUT HSYNC VSYNC FIELD 9 HMP8117 Pixel Port Timing The the timing and format of the output data and control signals is presented in the following sections. Refer to the section “CYCLE SLIPPING AND REAL-TIME PIXEL JITTER” for PLL and interface considerations. HSYNC and VSYNC Timing 2 ...
Page 10
... Table 3 for typical blanking programming values. During active scan lines, BLANK is asserted when the horizontal pixel count matches the value in the START H_BLANK register 31 /30 . The pixel counter is 000 HMP8117 264 265 266 267 261 262 263 264 265 ‘ ...
Page 11
... P13 Y5, Cb5, Cr5 [D5] P14 Y6, Cb6, Cr6 [D6] P15 Y7, Cb7, Cr7 [D7] NOTE: 5. Definitions in brackets are port definitions during raw VBI data transfers. Refer to the section on teletext for more information on raw VBI. 11 HMP8117 ODD FIELD SYNC AND BACK PORCH VERTICAL BLANKING EVEN FIELD FRONT ...
Page 12
... FIGURE 9. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 1) 12 HMP8117 Cr Y′...], with the first active data each scan line containing Cb data. The pixel output timing is shown in Figures 8 and 9. BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD are output following the rising edge of CLK2 ...
Page 13
... R 0 [P14-P10] P10-P5 G0 [P9-P5] P4- DVLD NOTE: 11. BLANK is asserted per Figure 7. FIGURE 11. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 0) 13 HMP8117 Cr0 Cb2 Cr2 and Cr are first active chrominance pixel data in a line. Cb and Cr will alternate every ...
Page 14
... CLK2. The BT.656 EAV and SAV formats are shown in Table 5 and the pixel output timing is shown in Figure 14. The EAV and SAV timing is determined by the programmed horizontal and vertical blank timing. BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD are output following the rising edge of CLK2. 14 HMP8117 ...
Page 15
... V: “1” during vertical blanking 23. H: “0” at SAV (start of active video); “1” at EAV (end of active video) Advanced Features In addition to digitizing an analog video signal the HMP8117 has hardware to process different types of Vertical Blanking Interval (VBI) data as described in the following sections. ...
Page 16
... WSS information are monitored. If WSS is enabled and WSS data is present, the WSS data is loaded into the WSS data registers. 16 HMP8117 DETECTION OF WSS The WSS decoder monitors the appropriate scan lines looking for the run-in and start codes used by WSS. If found, ...
Page 17
... WSS_EVEN_A and WSS_EVEN_B registers set to “0” after the data has been read out. BT.656 Ancillary Data Through the BT.656 interface the HMP8117 can generate non-active video data which contains CC, WSS, teletext or CLK VBIVALID ...
Page 18
... WSS CRC data = “00 0000” during PAL operation. 30. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored. Teletext The HMP8117 supports ITU-R BT.653 625-line and 525-line teletext system B, C and D capture. NABTS (North American Broadcast Teletext Specification) is the same as BT.653 525-line system C, which is also used to transmit Intel Intercast™ ...
Page 19
... VBI data, excluding the equalization and serration lines. The start and end timing of capturing “raw” VBI data on a scan line is determined by the Start and End Raw VBI 19 HMP8117 DATA PACKET Bit 0 FIGURE 16. TELETEXT VBI VIDEO SIGNAL P14 ...
Page 20
... When the interface is not active, SCL and SDA must be pulled high using external 4kΩ pull-up resistors. The SA input pin determines the slave address for the HMP8117. If the SA pin is pulled low, the address is 1000100x up resistor, the address is 1000101x address is the I Data is placed on the SDA line when the SCL line is low and held stable when the SCL line is pulled high ...
Page 21
... In order to perform a read from a specific control register 2 within the HMP8117 bus write must first be performed to properly setup the address register. Then bus read can be performed to read from the desired control register(s result of needing the write cycle for a ...
Page 22
... AGC Hysteresis H 7F Device Revision H Sub-Addresses -4F are reserved. Reads from these registers may return non-zero values Sub-Addresses - HMP8117 TABLE 10. CONTROL REGISTER SUMMARY RESET/ DEFAULT USE VALUE VALUE ...
Page 23
... Output Color 00 = Normal operation10 = Output black field Select 01 = Output blue field11 = Output 75% color bars 0 Reserved Set to “0” for proper operation. Vertical Pixel Siting control is not supported. 23 HMP8117 TABLE 11. PRODUCT ID REGISTER SUB ADDRESS = 00 H DESCRIPTION TABLE 12. INPUT FORMAT REGISTER SUB ADDRESS = 01 H ...
Page 24
... Detect Select acquisition mode pulses pulse 1-0 CLK2 Frequency This bit indicates the frequency of the CLK2 input clock 24.54MHz10 = 29.5MHz 01 = 27.0MHz11 = Reserved 24 HMP8117 TABLE 14. OUTPUT CONTROL REGISTER SUB ADDRESS = 03 H DESCRIPTION TABLE 15. GENLOCK CONTROL REGISTER SUB ADDRESS = 04 H DESCRIPTION RESET ...
Page 25
... To avoid color shifts when changing contrast, this bit should be a “1” Contrast controls only Y data 1 = Contrast controls Y and CbCr data 0 Color Low-Pass This bit selects the bandwidth of the CbCr data. Filter Select 0 = 850kHz 1 = 1.5MHz 25 HMP8117 SUB ADDRESS = 05 H DESCRIPTION TABLE 17. COLOR PROCESSING REGISTER SUB ADDRESS = 06 H DESCRIPTION RESET STATE ...
Page 26
... WSS enabled for both odd and even fields 3-2 Sliced Teletext 00 = Teletext disabled10 = Teletext system C enabled Enable 01 = Teletext system B enabled11 = Teletext system D enabled 1-0 Reserved 26 HMP8117 TABLE 18. LUMA PROCESSING REGISTER SUB ADDRESS = 08 H DESCRIPTION SUB ADDRESS = 0A H DESCRIPTION ) PAL C ) PAL ...
Page 27
... If set to “1”, Wide Screen Signalling (WSS) data is detected on the even field. 3 VBI Teletext This bit is read-only. Data written to this bit is ignored. Detect Status If set to “1”, Teletext data is detected during the vertical blanking interval. 2-0 Reserved 27 HMP8117 SUB ADDRESS = 0B H DESCRIPTION 2 C interface is always available interface is always available interface ...
Page 28
... If set to “1”, an interrupt is enabled for the successful auto detection of a video standard. Video Standard Interrupt Mask 0 Vertical Sync If set to “1”, an interrupt is enabled for the start of a new field. Interrupt Mask 28 HMP8117 TABLE 22. VIDEO STATUS REGISTER SUB ADDRESS = 0E H DESCRIPTION bit 4. H TABLE 23. INTERRUPT MASK REGISTER ...
Page 29
... If set to “1”, odd field lines are converted to RAW VBI data as specified by the RAW VBI All bit Odd Field and the RAW VBI LINE MASK registers. If set to “0”, the odd field lines are excluded from the RAW VBI data stream. 29 HMP8117 TABLE 24. INTERRUPT STATUS REGISTER SUB ADDRESS = 10 H DESCRIPTION . To clear the interrupt request, a “ ...
Page 30
... NO. FUNCTION 7-3 Reserved 2-0 Raw VBI Line A “1” in each bit position enables raw VBI capture for a corresponding input video line. Refer to Mask_18_16 Table 32 below. 30 HMP8117 TABLE 26. RAW VBI START COUNT REGISTER SUB ADDRESS = 12 H DESCRIPTION SUB ADDRESS = 13 H DESCRIPTION SUB ADDRESS = 14 H DESCRIPTION TABLE 29 ...
Page 31
... A value of 1x (“0100 0000”) has no effect on the data. This register enabled by the selection of “fixed gain control” mode in the Color Processing register 06 31 HMP8117 TABLE 32. RAW VBI MASK DEFINITIONS MASK_15_8 (Register 16 ...
Page 32
... Specifies the amount of high frequency gain control for luminance signals (either 2.6MHz or Adjust determined by the Luma Processing register 08 SC 1111 ) to -12dB (00 0100 B 32 HMP8117 TABLE 38. VIDEO GAIN ADJUST REGISTER SUB ADDRESS = 1D H DESCRIPTION bits 7-4. The value of this register selects a combined analog attenuation and a H TABLE 39. VIDEO GAIN REGISTER LOOKUP TABLE Video Reg ...
Page 33
... If even field captioning is enabled and present, this register is loaded with the first eight bits of Caption Data caption data on line 281, 284, or 335. Bit 0 corresponds to the first bit of caption information. Data written to this register is ignored. 33 HMP8117 TABLE 41. HOST CONTROL REGISTER SUB ADDRESS = 1F H DESCRIPTION ...
Page 34
... Reserved 13-8 Even Field If even field WSS is enabled and present, this register is loaded with the second six bits of WSS WSS Data information on line 280, 283, or 336. Data written to this register is ignored. 34 HMP8117 SUB ADDRESS = 23 H DESCRIPTION TABLE 46. WSS_ODD_A DATA REGISTER SUB ADDRESS = 24 H DESCRIPTION TABLE 47 ...
Page 35
... FUNCTION 15-9 Reserved 8 Assert BLANK This 1-bit register is cascaded with Start V_BLANK Low Register to form a 9-bit start vertical Output Signal blank register. 35 HMP8117 TABLE 51. WSS_CRC_EVEN DATA REGISTER SUB ADDRESS = 29 H DESCRIPTION TABLE 52. START H_BLANK LSB REGISTER SUB ADDRESS = 30 H DESCRIPTION TABLE 53. START H_BLANK MSB REGISTER ...
Page 36
... Defines the minimum number of fields that an MV component must be present for in order to Field Count change the MV Detection Status of register 0E count. Ex: The default of 110 BIT NO. FUNCTION 7-0 Reserved Set bits 5 HMP8117 TABLE 57. END V_BLANK REGISTER SUB ADDRESS = 35 H DESCRIPTION TABLE 58. END HSYNC REGISTER SUB ADDRESS = 36 H DESCRIPTION . H TABLE 59 ...
Page 37
... Set to 0000 BIT NO. FUNCTION 7-0 Device Revision This 8-bit register specifies the device revision number. Data written to this read-only register is ignored. The production baseline revision number HMP8117 SUB ADDRESS = 50 H DESCRIPTION for proper operation. TABLE 63. MV STRIPE GATE SUB ADDRESS = 51 H DESCRIPTION for proper operation ...
Page 38
... O External Anti- Alias Filter YIN 75Ω Term, 1μF AC-coupled I External Anti- Alias Filter A/D TEST 17 O RSET AGND REF_CAP AGND 38 HMP8117 80 LEAD PQFP TOP VIEW YIN 8 OUT ...
Page 39
... HMP8117 Storage capacitor for Luminance signal DC restoration. The LCAP voltage offsets the sync 0.1µF tip to the lower reference of the A/D. A 0.1μF capacitor should be connected between this pin and AGND. This capacitor should be as close to this pin as possible for best performance ...
Page 40
... HMP8117 implement the lowest possible noise on the power and ground planes by providing excellent decoupling. The optimum layout places the HMP8117 as close as possible to the power supply connector and the video input connector. Place external components as close as possible to the appropriate pin using short, wide traces. ...
Page 41
... Application Notes are also available on the Intersil Multimedia web site at http://www.intersil.com/mmedia. AN9644: Composite Video Separation Techniques AN9716: Wide Screen Signalling AN9717: YCbCr to RGB Considerations AN9728: BT.656 Video Interface for ICs AN9806: Advantages of the HMP8117 Videolyzer Operation EXTERNAL 75Ω VIDEO SOURCES 75 VID1 75 ...
Page 42
... Output Logic Low Voltage 42 HMP8117 Thermal Information Thermal Resistance (Typical, See Note 41) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 0.5V CC Maximum Power Dissipation HMP8117CN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.78W Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Maximum Junction Temperatures . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Lead Temperature (Soldering 10s +300°C = 5.0V +25° SYMBOL ...
Page 43
... Video Input Bandwidth ADC Input Range A IN ADC Integral Nonlinearity ADC Differential Nonlinearity VIDEO PERFORMANCE Differential Gain Differential Phase Hue Accuracy Color Saturation Accuracy Luminance Nonlinearity SNR SNRL 43 HMP8117 = 5.0V +25°C (Continued SYMBOL TEST CONDITION Max, Input = ...
Page 44
... OL 44. Since the HMP8117 does not generate the sample clock, any clock jitter present on the CLK2 input will directly translate to pixel jitter on the output data. The Vertical Sample Alignment parameter specifies the spatial pixel alignment from one scan line to the next using a stable CLK2 source ...
Page 45
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 45 HMP8117 Q80.14x20 80 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE SYMBOL ...