hmp8117 Intersil Corporation, hmp8117 Datasheet - Page 14

• Manufacturer Part Number: hmp8117
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

NOTES:
NOTES:
8-Bit BT.656 Output
For the BT.656 output mode, data is output following each
rising edge of CLK2. The BT.656 EAV and SAV formats are
shown in Table 5 and the pixel output timing is shown in
Figure 14. The EAV and SAV timing is determined by the
programmed horizontal and vertical blank timing.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2.
12. Y
13. BLANK is asserted per Figure 7.
14. DVALID is asserted for every valid pixel during both active and blanking regions.
15. BLANK is asserted per Figure 7.
16. DAVLID is asserted for every valid pixel during both active and blanking regions. DVALID is not a 50% duty cycle synchronous output and will
to the 4:2:2 subsampling.
appear to jitter as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs.
0
[P14-P10]
DVALID
P15-P8
P15-P11
is the first active luminance pixel of a line. Cb
[P9-P5]
P10-P5
P4-P0
P7-P0
DVALID
BLANK
CLK
CLK
FIGURE 13. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 1)
FIGURE 12. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 1)
14
t
DVLD
t
DVLD
0
Y
Cb
and Cr
0
R0
G
B
0
0
0
0
are first active chrominance pixels in a line. Cb and Cr will alternate every cycle due
HMP8117
Y
Cr
1
R
G
B
0
1
1
0
During the blanking intervals, the YCbCr outputs have a
value of 16 for Y and 128 for Cb and Cr, unless ancillary data
is present.
Y
Cb
2
R
G
B
2
2
2
2
Y
Cr
3
B
R
G
2
3
3
2
April 19, 2007
Y
Cb
4
B
R
G
4
4
4
4
FN4643.3