hmp8190 Intersil Corporation, hmp8190 Datasheet
hmp8190
Related parts for hmp8190
hmp8190 Summary of contents
Page 1
... Data Sheet NTSC/PAL Video Encoder The HMP8190 and HMP8191 are NTSC and PAL encoders designed for use in systems requiring the generation of high- quality NTSC and PAL video. YCbCr digital video data drive the P0-P15 inputs. The Y data is optionally lowpass filtered to 6MHz and drives the Y analog output. Cb and Cr are each lowpass fi ...
Page 2
... HMP8190, HMP8191 2 ...
Page 3
... Both accept YCbCr digital video input data and generate analog video output signals. The three outputs are one composite video signal and Y/C (S-Video). The HMP8190/HMP8191 accepts pixel data in one of several formats and transforms it into 4:4:4 sampled luminance and chrominance (YCbCr) data. The encoder then interpolates the YCbCr data to twice the pixel rate and low pass filters it to match the bandwidth of the video output format ...
Page 4
... The format of the SAV and EAV codes are shown in Table 3. The BT.656 input may also include ancillary data to load the VBI or RTCI data registers. The HMP8190/HMP8191 will use the ancillary data when enabled in the VBI data input and timing I/O registers. The ancillary data formats and the enable registers are described later in this datasheet ...
Page 5
... Start Active Video End Active Video P3 - P0: Protection bits; Ignored Video Timing Control The pixel input data and the output video timing of the HMP8190/HMP8191 are 59.94 fields per second interlaced. The timing is controlled by the BLANK, HSYNC, VSYNC, FIELD, and CLK2 pins. HSYNC, VSYNC, and Field Timing The leading edge of HSYNC indicates the beginning of a horizontal sync interval ...
Page 6
... BLANK is asserted. There may be an additional 0-3 CLK2 delays in modes which use CLK. The data pipeline delay through the HMP8190/HMP8191 is 26 CLK2 cycles. In operating modes which use CLK to gate the inputs into the encoder, the delay may be an additional 0- 7 CLK2 cycles ...
Page 7
... Y data to 6.0MHz. Lowpass filtering Y removes any aliasing artifacts due to the upsampling process, and simplifies the analog output filters. The Y 6.0MHz lowpass filter response is shown in Figure 8. At this point, the HMP8190/HMP8191 also scales the Y data to generate the proper output levels for the various video standards. ...
Page 8
... When the PHINC source is BT.656 data, the SCH phase reset should be disabled. If enabled, the HMP8190/HMP8191 resets the NCO periodically to avoid an accumulation of SCH phase error. The reset occurs at the beginning of each field to burst phase sequence. The sequence repeats every 4 fields for NTSC or 8 fi ...
Page 9
... If the registers are not updated, the encoder resends the previously loaded values. The HMP8190/HMP8191 provides a write status bit for each WSS line. The encoder clears the write status bit to ‘0’ when 2 C interface WSS is enabled and all bytes of the WSS data register have been written. The encoder sets the write status bit to ‘ ...
Page 10
... CRC P14# NOTE: The even parity (EP and EP#) bits are ignored. Line = Data Register Select Line 20 283. The WSS CRC data bits are ignored during PAL operation but must be included in the transfer Don’t Care. 10 HMP8190, HMP8191 P14 P13 P12 ...
Page 11
... EP (8 Nibbles CRC P14# NOTE: The even parity (EP and EP#) bits are ignored. HPLL, PSW, F2, and F1 are ignored Don’t Care. 11 HMP8190, HMP8191 TABLE 9. WIDESCREEN SIGNALLING MODES WSS REGISTERS 283A, 283B, CRC283 Ignored Ignored WSS Data WSS Data P14 P13 P12 ...
Page 12
... RSET must be chosen such that the maximum output current is not exceeded. These limits are listed in the Electrical Specifications section below. If the VREF pin is not connected, the HMP8190/HMP8191 uses the internal reference voltage. Otherwise, the applied voltage overdrives the internal reference external reference is used, it must decoupled from any power supply noise ...
Page 13
... SUB ADDR 0x40 OR 0x42 DATA READ S CHIP ADDR A SUB ADDR 0x40 OR 0x42 FIGURE 11. REGISTER WRITE PROGRAMMING FLOW 13 HMP8190, HMP8191 TABLE 11. CONTROL REGISTER NAMES CONTROL REGISTER product ID output format input format video processing timing I/O 1 timing I/O 2 VBI data enable VBI data input reserved ...
Page 14
... Lower limit of composite active video is about half the sync height 5 SCH Phase 0 = Never reset SCH phase Mode 1 = Reset SCH phase every 4 (NTSC (PAL) fields 4-0 Reserved 14 HMP8190, HMP8191 TABLE 12. PRODUCT ID REGISTER SUB ADDRESS = 00 H DESCRIPTION TABLE 13. OUTPUT FORMAT REGISTER SUB ADDRESS = 01 H DESCRIPTION TABLE 14 ...
Page 15
... Reserved 1-0 Subcarrier PHINC Selects the source of the color subcarrier NCO phase increment value. Select 00 = Internal (fixed) data Reserved 10 = BT.656 RTCI ancillary data HMP8190, HMP8191 TABLE 16. TIMING I/O REGISTER #1 SUB ADDRESS = 04 H DESCRIPTION TABLE 17. TIMING I/O REGISTER #2 SUB ADDRESS = 05 H DESCRIPTION 2 C interface PHINC register ...
Page 16
... WSS_20A, WSS_20B, CRC_20A, and CRC_20B data registers contain Line 20 unused data Write Status 1 = Data has been output, host processor may now write to the registers 16 HMP8190, HMP8191 TABLE 18. AUXILIARY DATA ENABLE REGISTER SUB ADDRESS = 06 H DESCRIPTION TABLE 19. VBI DATA INPUT REGISTER SUB ADDRESS = 07 ...
Page 17
... This register is cascaded with the closed caption_21A data register and they are read out se- MSB Data rially as 16 bits during line 18, 21 line 21 captioning is enabled. Bit D0 of the 21A data register is shifted out first. 17 HMP8190, HMP8191 SUB ADDRESS = 0E H DESCRIPTION TABLE 21. HOST CONTROL REGISTER 2 ...
Page 18
... This register is cascaded with the WSS_283A data register and they are read out serially as WSS MSB Data 14 bits during line 280, 283, or 336 if WSS is enabled. Bit D0 of the WSS_283A data register is shifted out first. 18 HMP8190, HMP8191 TABLE 24. CLOSED CAPTION_284A DATA REGISTER SUB ADDRESS = 12 H DESCRIPTION TABLE 25 ...
Page 19
... This 8-bit register specifies the horizontal count (in 1x clock cycles) at which to start inputting Output Signal pixel data each scan line. The leading edge of HSYNC is count 000 (Horizontal) unless BLANK is configured as an output. 19 HMP8190, HMP8191 TABLE 30. CRC_20 REGISTER SUB ADDRESS = 18 H DESCRIPTION TABLE 31. CRC_283 REGISTER ...
Page 20
... Select the field and to reset the half line counter ignored unless HSYNC and VSYNC are config- ured as inputs leading edge 1 = trailing edge 20 HMP8190, HMP8191 TABLE 35. START V_BLANK LOW REGISTER SUB ADDRESS = 23 H DESCRIPTION TABLE 36. START V_BLANK HIGH REGISTER SUB ADDRESS = 24 ...
Page 21
... PHINC value is the phase increment value of the color subcarrier generation NCO. When the BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to determine the last PHINC value loaded via the selected interface. 21 HMP8190, HMP8191 TABLE 39. FIELD CONTROL REGISTER 2 SUB ADDRESS = 27 H DESCRIPTION TABLE 40 ...
Page 22
... INPUT/ NAME NUMBER OUTPUT P0-P15 58, 55-43, 38 32-27, 23, 22 RESV 21 FIELD 34 HSYNC 35 VSYNC 36 BLANK 33 CLK 39 CLK2 41 22 HMP8190, HMP8191 HMP8190/HMP8191 (PQFP) TOP VIEW VAA 1 VAA GND 4 VAA 5 GND GND 8 VAA 9 GND 10 11 ...
Page 23
... NTSC/PAL 11 VREF 61 FS_ADJUST 62 COMP 1 64 COMP 2 63 VAA GND 23 HMP8190, HMP8191 Interface Clock Input. The circuit for this pin should include a 4-6k pull-up resistor con- nected to VAA Interface Address Select Input Interface Data Input/Output. The circuit for this pin should include a 4-6k pull-up resis- tor connected to VAA ...
Page 24
... Differential Nonlinearity, DNL Output Current Output Impedance Output Capacitance Output Compliance Range Video Level Error Internal Voltage Reference 24 HMP8190, HMP8191 Thermal Information Thermal Resistance (Typical, Note 4) + 0.5V) PQFP Package Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 Maximum Storage Temperature Range . . . . . . . . . . -65 Vapor Phase Soldering, 1 Minute . . . . . . . . . . . . . . . . . . . . . .220 ...
Page 25
... OUT 8. If using an external voltage reference not powered down. The internal voltage reference is powered down. 25 HMP8190, HMP8191 A TEST CONDITION VREF = 1.230V (Figure 27), RSET = 140 Pin not connected, using internal reference Pin connected to external reference. Using analog output filter shown in Figure 28A SCH Phase Reset enabled Using analog output filter shown in Figure 28A ...
Page 26
... NOISE LEVEL = -79.9dB RMS -35.0 -40.0 -45.0 -50.0 -55.0 -60.0 -65.0 -70.0 -75.0 -80.0 -85.0 -90.0 -95.0 -100.0 1.0 2.0 3.0 AVERAGE (MHz) FIGURE 12. NOISE SPECTRUM (NTSC) 26 HMP8190, HMP8191 APL = 44.3% 4.0 5.0 SETUP 7.5% FIGURE 13. NTSC COLOR BAR VECTOR SCOPE PLOT FIGURE 14. NTSC FCC COLOR BAR SYSTEM LINE ANGLE (DEG) 0.0 GAIN x1.000 0.000dB 525 LINE NTSC BURST FROM SOURCE ...
Page 27
... AVERAGE FIGURE 15. LUMINANCE NON LINEARITY (NTSC) LINE JITTER (LINE 20 TO 250) FIGURE 17. H SYNC JITTER IN A FRAME (NTSC) AVERAGE FIGURE 19. NOISE SPECTRUM (PAL) 27 HMP8190, HMP8191 (Continued) wfm ---> 5 STEP PEAK-TO-PEAK = 2.1 LINE FREQUENCY ERROR 100.0 99.8 -0.4 LINE FREQUENCY 15.734 (kHz) FIELD FREQUENCY 59.94 (Hz) ...
Page 28
... AVERAGE FIGURE 22. LUMINANCE NON LINEARITY (PAL) 28 HMP8190, HMP8191 (Continued) FIGURE 21. COLORBAR (PAL) wfm ---> 5 STEP PEAK-TO-PEAK = 1.4 LINE FREQUENCY ERROR 100.0 99.8 -0.4 LINE FREQUENCY 15.625 (kHz) FIELD FREQUENCY 50.00 (Hz) AVERAGE OFF 4TH 5TH Wfm ---> COLOR BAR 0.00 (%) -0.2 0.0 0.2 (%) FIGURE 23. LINE FREQUENCY (PAL) ...
Page 29
... A common ground plane for all devices, including the HMP8190/HMP8191, is recommended. However, placing the encoder on an electrically connected GND peninsula reduces noise levels. All GND pins on the HMP8190/HMP8191 must be connected to the ground plane. Typical power and ground planes are shown in Figure 26. ...
Page 30
... FIGURE 26. EXAMPLE POWER AND GROUND PLANES Analog Output Filters The various video standards specify the frequency response of the video signal. The HMP8190/HMP8191 uses 2X oversampling DACs to simplify the reconstruction filter required. Example post filters are shown in Figure 28. The analog output filters should be as close as possible to the HMP8190/HMP8191 ...
Page 31
... The board allows the encoder’s operation and performance to be observed and measured. The HMP8190EVAL1 board has a 50 pin, two row receptacle which allows connection into an existing system. The connector provides access to all of the encoder’s digital inputs and outputs ...
Page 32
... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 32 HMP8190, HMP8191 Q64.14x14 64 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE SYM- -B- e SEATING PLANE A NOTES: 1 ...