hmp8190 Intersil Corporation, hmp8190 Datasheet - Page 4

• Manufacturer Part Number: hmp8190
• Description: Ntsc/pal Video Encoder
• Manufacturer: Intersil Corporation

8-Bit YCbCr Format
When 8-bit YCbCr format is selected, the data is latched on
each rising edge of CLK2. The pixel data must be [Cb Y Cr
Y’ Cb Y Cr Y’ . . . ], with the first active data each scan line
being Cb data. The pixel input timing is shown in Figure 1.
As inputs, BLANK, HSYNC, and VSYNC are latched on
each rising edge of CLK2. As outputs, BLANK, HSYNC, and
VSYNC are output following the rising edge of CLK2. If the
CLK pin is configured as an input, it is ignored. If configured
as an output, it is one-half the CLK2 frequency.
16-Bit YCbCr Format
When 16-bit YCbCr format is selected, the pixel data is
latched on the rising edge of CLK2 while CLK is low. The
pixel input timing is shown in Figure 2.
As inputs, BLANK, HSYNC, and VSYNC are latched on the
rising edge of CLK2 while CLK is low. As outputs, HSYNC,
VSYNC, and BLANK are output following the rising edge of
CLK2 while CLK is high. In these modes of operation, CLK is
one-half the CLK2 frequency.
(OUTPUT)
(OUTPUT)
(INPUT)
BLANK
BLANK
P8-P15
CLK2
(INPUT)
P0-P7
BLANK
BLANK
P8-P15
CLK
CLK2
4
Cb 0
Y 0
Cb 0
FIGURE 2. PIXEL INPUT TIMING - 16-BIT YCBCR
FIGURE 1. PIXEL INPUT TIMING - 8-BIT YCBCR
Cr 0
Y 1
Y 0
HMP8190, HMP8191
Cb 2
Y 2
Cr 0
Cr 2
Y 3
Y 1
8-Bit BT.656 Format
When BT.656 format is selected, data is latched on each
rising edge of CLK2. The pixel input timing is shown in
Figure 3. The figure shows the EAV code at the end of the
line. The format of the SAV and EAV codes are shown in
Table 3.
The BT.656 input may also include ancillary data to load the
VBI or RTCI data registers. The HMP8190/HMP8191 will
use the ancillary data when enabled in the VBI data input
and timing I/O registers. The ancillary data formats and the
enable registers are described later in this datasheet.
As inputs, the BLANK, HSYNC, and VSYNC pins are
ignored since all timing is derived from the EAV and SAV
sequences within the data stream. As outputs, BLANK,
HSYNC and VSYNC are output following the rising edge of
CLK2. If the CLK pin is configured as an input, it is ignored. If
configured as an output, it is one-half the CLK2 frequency.
Cb 4
Cb 2
Y 4
Cr 4
Y 5
Y 2
Cr N-1
Y N
Y N