at42qt1070 ATMEL Corporation, at42qt1070 Datasheet - Page 32

• Manufacturer Part Number: at42qt1070
• Description: Qtouch 7-channel Sensor Ic
• Manufacturer: ATMEL Corporation

A.4
A.5
32
Address Byte Format
Data Byte Format
AT42QT1070
Figure A-3.
All address bytes are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and
an acknowledge bit. If the READ/WRITE bit is set, a read operation is performed, otherwise a
write operation is performed. When the device recognizes that it is being addressed, it will
acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. An address byte consisting of a
slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively.
The most significant bit of the address byte is transmitted first. The address sent by the host
must be consistent with that selected with the option jumpers.
Figure A-4.
All data bytes are 9 bits long, consisting of 8 data bits and an acknowledge bit. During a data
transfer, the host generates the clock and the START and STOP conditions, while the Receiver
is responsible for acknowledging the reception. An acknowledge (ACK) is signaled by the
Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line
high, a NACK is signaled.
SDA
SCL
START and STOP Conditions
Address Byte Format
START
Addr MSB
SDA
SCL
1
START
2
Addr LSB
7
STOP
R/W
8
ACK
9
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