lm2502sm National Semiconductor Corporation, lm2502sm Datasheet - Page 22

• Manufacturer Part Number: lm2502sm
• Description: Mobile Pixel Link Mpl Display Interface Serializer And Deserializer
• Manufacturer: National Semiconductor Corporation

www.national.com
Application Information
MPL SWAP FEATURE
The LM2502 provides a swap function of MPL MD lines
depending upon the state of the M/S* pin. This facilitates a
straight through MPL interface design eliminating the needs
for via and crossovers as shown on Figure 17 . See also
Connection Diagram and Table 1 .
Note that three pins are defined differently on the MAS-
TER and the SLAVE configured device. Schematic Cap-
ture device diagrams should take this into account for
proper connection. The following pin descriptions apply
for the three pins given in Ball Number : Master (Slave)
function
UFBGA Package
LLP Package
FLEX CIRCUIT RECOMMENDATIONS
The three MPL lines should generally run together to mini-
mize any trace length differences (skew). For impedance
control and also noise isolation (crosstalk), guard ground
traces are recommended in between the signals. Commonly
a Ground-Signal-Ground (GSGSGSG) layout is used. Lo-
cate fast edge rate and large swing signals further away to
also minimize any coupling (unwanted crosstalk). In a
stacked flex interconnect, crosstalk also needs to be taken
into account in the above and below layers (vertical direc-
tion). To minimize any coupling locate MPL traces next to a
ground layer. Power rails also tend to generate less noise
than LVCMOS so they are also good candidates for use as
isolation and separation.
The interconnect from the Master to the Slave typically acts
like a transmission line. Thus impedance control and ground
• A5 : INTR (CLKDIS*)
• A6 : MD1 (MD0)
• B7 : MD0 (MD1)
• 34 : INTR (CLKDIS*)
• 32 : MD1 (MD0)
• 29 : MD0 (MD1)
FIGURE 17. MPL Interface Layout - UFBGA Example
(Continued)
22
returns are an important part of system design. Impedance
should be in the 50 to 100 Ohm nominal range for the
LM2502. Testing has been done with cables ranging from 40
to 110 Ohms without error (BER Testing). To obtain the
impedance, adjacent grounds are typically required ( 1 layer
flex), or a ground shield / layer. Total interconnect length is
intended to be in the 20cm range, however 30cm is possible
at lower data rates. Skew should be less than 500ps to
maximize timing margins.
GROUNDING
While the LM2502 employs three separate types of ground
pins, these are intended to be connected together to a
common ground plane. The separate ground pins help to
isolate switching currents from different sections of the inte-
grated circuit (IC). Also required is a nearby signal return
(ground) for the MPL signals. These should be provided next
to the MPL signals, as that will create the smallest current
loop area. The grounds are also useful for noise isolation
and impedance control.
PCB RECOMMENDATIONS
General guidelines for the PCB design:
• Floor plan, locate MPL Master near the connector to limit
• Route serial traces together, minimize the number of
• Use ground lines are guards to minimize any noise cou-
• Avoid parallel runs with fast edge, large LVCMOS swings.
• Also use a GSGSG pinout in connectors (Board to Board
• Slave device - follow similar guidelines.
• Bypass the device with MLC surface mount devices and
• High current returns should have a separate path with a
chance of cross talk to high speed serial signals.
layer changes to reduce loading.
pling (guarantees distance).
or ZIF).
thinly separated power and ground planes with low induc-
tance feeds.
width proportional to the amount of current carried to
minimize any resulting IR effects.
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