cbtl12131 NXP Semiconductors, cbtl12131 Datasheet
cbtl12131
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cbtl12131 Summary of contents
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... DisplayPort v1.1a interconnect. All switch and configuration settings can be performed by board-strapping or driving simple CMOS inputs—no software or bus configuration is required. CBTL12131 is available × Product data sheet ...
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... AUX channel bias control inputs for Port B to allow configuration as source or sink CBTL12131 Product data sheet DisplayPort multiplexer for bidirectional video 2 C-bus multiplexing All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 © NXP B.V. 2011. All rights reserved ...
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... DisplayPort PORT C dual through mode DisplayPort PORT A CBTL12131 in typical system configuration Description plastic thin fine-pitch ball grid array package; 64 balls; body 6 × 6 × 0.8 mm All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 DisplayPort multiplexer for bidirectional video ...
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... R AUX100_N R AUX4M7N 4.7 MΩ AUX HPD TERMINATION FILTER CONFIGURATION All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 DisplayPort multiplexer for bidirectional video 4 R PD_HPD PATH_SEL 200 kΩ AUX4M7P 4.7 MΩ PATH_SEL = 0: R PD_HPD High-Z 200 kΩ ...
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... ML_C_2N ML_C_3N VDD GND ML_C_2P ML_C_3P HPD_C HPD_A Port C All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 DisplayPort multiplexer for bidirectional video CBTL12131ET 002aae675 Transparent top view Port B (faces external DP connector) ...
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... Product data sheet DisplayPort multiplexer for bidirectional video Description Input to set the path configuration of the CBTL12131. When LOW, Ports A and B are mutually connected, as well as Ports C and D. When HIGH, Port B is connected to Port D. Input to select between DDC and AUX terminals for Port A. When HIGH, the DDC_A_P and DDC_A_N terminals are connected to their respective AUX_B_P and AUX_B_N terminals on Port B ...
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... DP or ++DP sink). When PATH_SEL = HIGH, HPD_B is configured as output and follows the state of HPD_D (from internal sink connected via DP connector to an external DP source. All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 © NXP B.V. 2011. All rights reserved ...
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... High-speed differential pair for DisplayPort AUX signals, Port tolerant HPD input for Port connected to the internal sink. 3.3 V power supply pins. Ground pins. All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 © NXP B.V. 2011. All rights reserved ...
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... One can select between two basic configurations: either Ports A and C are connected to Ports B and D respectively, or Port B is connected to Port D while Ports A and C are high-impedance. In addition, the CBTL12131 includes circuitry to assist in detection and configuration of Port B designated as the port facing the external DisplayPort connector ...
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Table 4. Main Link signal mappings Legend: high-Z = isolating, high-impedance; ACT = active, low-impedance active, equalized/re-driven. Inputs PATH_SEL HPD_B_FLT Port C - Port D ML_C_0P ACT ML_C_0N ACT ML_C_1P ACT ML_C_1N ACT 0 0 ML_C_2P ACT ML_C_2N ...
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... PATH_SEL = 1: off AUX_C PATH_SEL = 0: off PATH_SEL = 1: pass else: off AUX_A select between AUX and DDC DDC_A else: off All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 Figure 6). AUX_D AUX_B 002aae678 © NXP B.V. 2011. All rights reserved ...
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... HPD filtering function. PATH_SEL = 0: active PATH_SEL = 1: LOW HPD_C HPD_A HPD channel topology All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 DisplayPort multiplexer for bidirectional video Channel Port B - Port D DDC_A high-Z high-Z high-Z ...
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... Steady-state is shown only. A HIGH-to-LOW transition will be filtered (~4 ms delay). 7.5 AUX logic state detection CBTL12131 includes a helpful function to determine the DC state of the AUX_B_P and AUX_B_N pins thereby aiding in the detection of devices connected to the external DP connector. The DC state of these pins is output on pins AUX_B_P_STATE and AUX_B_N_STATE respectively, after the 1 Mbit/s (typ) Manchester-encoded bitstream is removed by filtering ...
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... Equalizer gain versus frequency Pre-emphasis settings Quinary notation All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 DisplayPort multiplexer for bidirectional video Equalizer mode (see Figure 3 EQ9.0 EQ6.5 EQ3.5 EQ2.0 EQ0.0 2 ...
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... DisplayPort multiplexer for bidirectional video Output voltage swing settings Quinary notation All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 Output mode 400 mV [1] 600 mV ] reserved reserved reserved © NXP B.V. 2011. All rights reserved ...
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... HDP when it is ready. When HPD_B_FLT is HIGH, this means the attached device is asserting HPD and CBTL12131 will activate its source type 100 kΩ termination resistors. When PATH_SEL is HIGH, this means the internal DisplayPort sink (embedded panel) is active, and its 1 MΩ ...
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... X X [1] HPD_B_FLT is an internally derived signal, not an input to CBTL12131. HPD_B_FLT will follow input HPD_B. [2] System controller will assert AUX_TERM_SNK HIGH when user action prompts a ‘toggle’, hence system should configure itself as a sink. [3] System controller will assert AUX_TERM_SRC HIGH when it has determined that a Sink is connected, hence system should configure itself as a source. ...
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... GND externally via a 10 kΩ accuracy resistor. The external resistor functions as a reference to establish accurate internal current sources for the EQ output stage. The second function of this pin is to put CBTL12131 in test mode by driving it HIGH. This test mode is for internal use only and has no use in normal operation. ...
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... Port D output; PATH_SEL = 1 LV5 short to GND LV5 10 kΩ resistor to GND Port D output; PATH_SEL = 1 PL5 short to GND PL5 10 kΩ resistor to GND All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 Min Typ Max Unit - ...
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... IH(max) Status output characteristics Parameter Conditions HIGH-level output voltage CMOS outputs LOW-level output voltage CMOS outputs transition time All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 DisplayPort multiplexer for bidirectional video Min −0.3 Figure 9 0. 1.5 [1] ...
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... 6.1 6.1 0.5 4.5 4.5 0.15 5.9 5.9 REFERENCES JEDEC JEITA MO-195 - - - All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 DisplayPort multiplexer for bidirectional video detail 0.08 0.05 0.1 EUROPEAN PROJECTION SOT543-1 ...
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... Solder bath specifications, including temperature and impurities CBTL12131 Product data sheet DisplayPort multiplexer for bidirectional video All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 © NXP B.V. 2011. All rights reserved ...
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... Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 11. All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 Figure 11) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...
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... Hot Plug Detect Inter-Integrated Circuit bus Input/Output Low Voltage Transistor-Transistor Logic Main Link All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 DisplayPort multiplexer for bidirectional video peak temperature time 001aac844 © NXP B.V. 2011. All rights reserved. ...
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... NXP Semiconductors 14. Revision history Table 22. Revision history Document ID Release date CBTL12131 v.1 20110225 CBTL12131 Product data sheet DisplayPort multiplexer for bidirectional video Data sheet status Change notice Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 © NXP B.V. 2011. All rights reserved ...
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... NXP Semiconductors’ product specifications. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 CBTL12131 © NXP B.V. 2011. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 25 February 2011 Document identifier: CBTL12131 ...