cbtl12131 NXP Semiconductors, cbtl12131 Datasheet - Page 13

• Manufacturer Part Number: cbtl12131
• Description: Cbtl12131 Displayport Multiplexer For Bidirectional Video In All-in-one Computer Systems
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 6.
[1]
CBTL12131
Product data sheet
PATH_SEL
Steady-state is shown only. A HIGH-to-LOW transition will be filtered (~4 ms delay).
0
0
0
0
1
1
HPD channel configuration
Inputs
HPD_B
n/a
n/a
0
0
1
1
7.5 AUX logic state detection
7.6 HPD logic state detection
7.7 Equalizer
CBTL12131 includes a helpful function to determine the DC state of the AUX_B_P and
AUX_B_N pins thereby aiding in the detection of devices connected to the external DP
connector. The DC state of these pins is output on pins AUX_B_P_STATE and
AUX_B_N_STATE respectively, after the 1 Mbit/s (typ) Manchester-encoded bitstream is
removed by filtering.
To further aid in detection of externally connected devices on Port B, the HPD_B_FLT pin
outputs a filtered version of pin HPD_B. The filtering function suppresses the 1 ms (typ)
LOW interrupt pulse from a DisplayPort sink, thereby avoiding a false disconnect
detection. Only a LOW pulse greater than 4 ms will result in a LOW output on
HPD_B_FLT.
The Equalizer function equalizes the signal on the Main Link channel of Port B and
re-drives them to Port D and ultimately to the internal display panel.
The Equalizer is only active when PATH_SEL is HIGH. When PATH_SEL is LOW, the
equalizer is effectively disabled and presents minimum parasitic load to the Main Link
channels.
The Equalizer has configurable Equalization (EQ) settings for its input (Port B side), which
can be set to one of five options by quinary input pin EQ5. See
options.
HPD_D
0
1
0
1
0
1
HPD_A
0
0
1
1
0
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
HPD_B
high-Z
high-Z
high-Z
high-Z
0
1
Outputs
HPD_B_FLT
0
0
1
1
0
1
DisplayPort multiplexer for bidirectional video
[1]
HPD_C
0
1
0
1
0
0
Normal mode; internal display
Normal mode; internal display
Normal mode but unexpected
Normal mode; with external sink
External source mode with
External source mode with
Comment
not (yet) asserting HPD
asserting HPD
condition; internal display not
asserting HPD during normal
operation
asserting HPD
internal display not (yet)
asserting HPD
internal display asserting HPD
Table 7
CBTL12131
© NXP B.V. 2011. All rights reserved.
for programming
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