mk50x256cmb100 Freescale Semiconductor, Inc, mk50x256cmb100 Datasheet

no-image

mk50x256cmb100

Manufacturer Part Number
mk50x256cmb100
Description
Arm Cortex-m4 Core With Dsp
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Freescale Semiconductor
Data Sheet: Product Preview
K50 Sub-Family Data Sheet
Supports the following:
MK50X256CLK100, MK50X256CMB100
Features
• Operating Characteristics
• Performance
• Memories and memory interfaces
• Clocks
• System peripherals
• Security and integrity modules
This document contains information on a product under development. Freescale
reserves the right to change or discontinue this product without notice.
© 2010–2011 Freescale Semiconductor, Inc.
Preliminary
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 85°C
– Up to 100 MHz ARM Cortex-M4 core with DSP
– Up to 512 KB program flash memory on non-
– Up to 256 KB program flash memory on
– Up to 256 KB FlexNVM on FlexMemory devices
– 4 KB FlexRAM on FlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
– FlexBus external bus interface
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
– 10 low-power modes to provide power optimization
– Memory protection unit with multi-master
– 16-channel DMA controller, supporting up to 64
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
– Hardware CRC module to support fast cyclic
– 128-bit unique identification (ID) number per chip
instructions delivering 1.25 Dhrystone MIPS per
MHz
FlexMemory devices
FlexMemory devices
based on application requirements
protection
request sources
redundancy checks
• Human-machine interface
• Analog modules
• Timers
• Communication interfaces
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
– Two 16-bit SAR ADCs
– Programmable gain amplifier (up to x64) integrated
– Two 12-bit DACs
– Two operational amplifiers
– Two transimpedance amplifiers
– Two analog comparators (CMP) containing a 6-bit
– Voltage reference
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
– Two 2-channel quadrature decoder/general purpose
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
– USB full-/low-speed On-the-Go controller with on-
– Two SPI modules
– Two I2C modules
– Four UART modules
– I2S module
into each ADC
DAC and programmable reference input
timer
timers
chip transceiver
K50P81M100SF2
Document Number: K50P81M100SF2
Rev. 4, 3/2011

Related parts for mk50x256cmb100

mk50x256cmb100 Summary of contents

Page 1

... Freescale Semiconductor Data Sheet: Product Preview K50 Sub-Family Data Sheet Supports the following: MK50X256CLK100, MK50X256CMB100 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 85°C • Performance – 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1 ...

Page 2

... DSPI switching specifications (low-speed mode)..58 6.8.5 DSPI switching specifications (high-speed mode) 59 6.8.6 I2C switching specifications..................................61 6.8.7 UART switching specifications..............................61 6.8.8 I2S switching specifications..................................61 6.9 Human-machine interfaces (HMI)......................................63 6.9.1 TSI electrical specifications...................................63 7 Dimensions...............................................................................64 7.1 Obtaining package dimensions.........................................64 8 Pinout........................................................................................64 8.1 K50 Signal Multiplexing and Pin Assignments..................65 8.2 K50 Pinouts.......................................................................69 Preliminary Freescale Semiconductor, Inc. ...

Page 3

... Revision History........................................................................70 K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 3 ...

Page 4

... K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 4 http://www.freescale.com Description • Fully qualified, general market flow • Prequalification • K50 • Program flash only • Program flash and FlexMemory Table continues on the next page... Preliminary and perform a part number Values Freescale Semiconductor, Inc. ...

Page 5

... An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Description • • • ...

Page 6

... Example This is an example of an attribute: Symbol Description CIN_D Input capacitance: digital pins K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 6 Min. Max. 0.9 1.1 Min. Max. 10 130 Min. Max. — 7 Preliminary Unit V Unit µA Unit pF Freescale Semiconductor, Inc. ...

Page 7

... Result of exceeding a rating Measured characteristic K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. –0.3 1.2 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating rating Preliminary Terminology and guidelines Max ...

Page 8

... This is an example of an operating behavior that includes a typical value: K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 8 Normal Limited operating operating range range - No permanent failure - No permanent failure - Correct operation - Possible decreased life - Possible incorrect operation Handling range - No permanent failure Preliminary Fatal range - Probable permanent failure ∞ Freescale Semiconductor, Inc. ...

Page 9

... Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol T Ambient temperature A V 3.3 V supply voltage DD 4 Ratings K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. Typ 1.00 1.05 1.10 V (V) DD Description Value 25 3.3 Preliminary Ratings Max ...

Page 10

... Min. -2000 -500 -100 Table continues on the next page... Preliminary Max. Unit Notes 150 °C 1 260 °C 2 245 Max. Unit Notes 3 — 1 Max. Unit Notes +2000 V 1 +500 V 2 +100 mA Min. Max. Unit –0.3 3.8 V — 185 mA –0.3 5.5 V Freescale Semiconductor, Inc. ...

Page 11

... V ≤ V ≤ 2 Input low voltage IL • 2.7 V ≤ V ≤ 3 • 1.7 V ≤ V ≤ 2 Input hysteresis HYS K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc Min. 1.71 1.71 –0.1 –0.1 1.71 0.7 × 0.75 × — — 0.06 × Table continues on the next page ...

Page 12

... TBD TBD Preliminary Max. Unit Notes –0.2 mA –5 mA — V — less than V IN Typ. Max. Unit Notes 1.1 TBD V 2.56 TBD V 2.70 TBD V 2.80 TBD V 2.90 TBD V 3.00 TBD 1.60 TBD V 1.80 TBD V 1.90 TBD V 2.00 TBD V 2.10 TBD 1.00 TBD V 1000 TBD μs Freescale Semiconductor, Inc The ...

Page 13

... R Internal pullup resistors PU R Internal pulldown resistors PD 1. Measured at VDD=3.6V 2. Measured at V supply voltage = Measured at V supply voltage = V DD K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. TBD Min. = -10mA V – 0 -3mA V – 0 -2mA V – ...

Page 14

... VLLSx→RUN recovery times in the following table Min. — DD — — — — — — — — — — — — Preliminary Max. Unit Notes 300 μs 1 4.1 μs 123.8 μs 4.1 μs 49.3 μs 4.1 μs 49.2 μs 4.1 μs 5.9 μs 4.1 μs 4.2 μs 4.1 μs 5.8 μs Freescale Semiconductor, Inc. ...

Page 15

... FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, and peripherals are in active operation. K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. Typ. ...

Page 16

... LVD disabled, USB regulator disabled • No GPIOs toggled • Code execution from flash Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled The following data was measured under these conditions: K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 16 Preliminary Freescale Semiconductor, Inc. ...

Page 17

... All peripheral clocks enabled but peripherals are not in active operation • LVD disabled, USB regulator disabled • No GPIOs toggled • Code execution from flash Figure 2. Run mode supply current vs. core frequency — all peripheral clocks enabled K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary General 17 ...

Page 18

... K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 18 Frequency band (MHz) 0.15–50 50–150 150–500 500–1000 0.15–1000 = 96 MHz SYS Table 8. Capacitance attributes Preliminary Typ. Unit Notes TBD dBμ TBD TBD TBD TBD — Min. Max. Unit — — Freescale Semiconductor, Inc. ...

Page 19

... Slew disabled • Slew enabled 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75pF load K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. Max. Normal run mode — 100 20 — ...

Page 20

... K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 20 Min. –40 – LQFP Unit MAPBGA TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Preliminary Max. Unit 125 °C 85 °C Notes °C/W 1 °C/W 1 °C/W 1 °C/W 1 °C/W 2 °C/W 3 °C/W 4 Freescale Semiconductor, Inc. ...

Page 21

... Clock and data fall time f T Data setup s T Data hold h Figure 3. TRACE_CLKOUT specifications TRACE_CLKOUT TRACE_D[3:0] Figure 4. Trace data specifications K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Frequency dependent 2 2 — — Preliminary Max ...

Page 22

... Max. Unit 2.7 3.6 V MHz 1/J1 — — 20 — 10 — — — ns — — — — ns — — 100 — — ns Min. Max. Unit 1.71 3.6 V MHz 1/J1 — ns Freescale Semiconductor, Inc. ...

Page 23

... TCLK low to TDO high-Z J13 TRST assert time J14 TRST setup time (negation) to TCLK high TCLK (input) K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Figure 5. Test clock input timing Preliminary Min ...

Page 24

... K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011 J11 J12 J11 Figure 7. Test Access Port timing Preliminary J5 J6 Input data valid Output data valid Output data valid J9 J10 Input data valid Output data valid Output data valid Freescale Semiconductor, Inc. ...

Page 25

... VDD and 25°C f Internal reference frequency (fast clock) — user intf_t trimmed K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors J14 Figure 8. TRST timing Table 13. MCG specifications Min. Typ. ...

Page 26

... MHz 2, 50 MHz 75 MHz 100 MHz — MHz 4, — MHz — MHz — MHz TBD ps TBD ps — — 100 MHz 950 — µA — 4.0 MHz 400 — — Freescale Semiconductor, Inc ...

Page 27

... Supply current — low-power mode (HGO=0) DDOSC • 32 kHz • 4 MHz • 8 MHz • 16 MHz • 24 MHz • 32 MHz K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. ± 1.49 — ± 4.47 — — ...

Page 28

... MΩ — MΩ — — MΩ 1 — MΩ — — kΩ 200 — kΩ — — kΩ 0 — kΩ 0.6 — — 0.6 — — Freescale Semiconductor, Inc ...

Page 29

... Table 16. 32kHz oscillator DC electrical specifications Symbol Description V Supply voltage BAT R Internal feedback resistor F C Parasitical capacitance of EXTAL32 and XTAL32 para K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. 32 — 3 — 8 — — — — ...

Page 30

... K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 30 Min. Typ. — 15 — 0.6 Min. Typ. Max. — 32 — — 1000 — Min. Typ. Max. — 20 TBD — 20 100 — 160 800 Preliminary Max. Unit — pF — V Unit Notes kHz ms 1 Unit Notes μ Freescale Semiconductor, Inc. ...

Page 31

... KB EEPROM backup t eewr8b64k • 128 KB EEPROM backup t eewr8b128k • 256 KB EEPROM backup t eewr8b256k K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — — — — — — — — ...

Page 32

... TBD Table continues on the next page... Preliminary Max. Unit Notes TBD μs TBD ms 1.5 ms TBD ms 2.5 ms TBD μs TBD ms 2.7 ms TBD ms 3.7 ms Typ. Unit 10 mA Max. Unit Notes 1 — years 2 — years 2 — years 2 — cycles 3 — years 2 Freescale Semiconductor, Inc. ...

Page 33

... The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. EEPROM – 2 × EEESPLIT × EEESIZE Writes_subsystem = K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min ...

Page 34

... EEESIZE — allocated FlexRAM based on DEPART; entered with Program Partition command • Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • n — data flash cycling endurance nvmcycd Figure 9. EEPROM backup writes to FlexRAM K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 34 Preliminary Freescale Semiconductor, Inc. ...

Page 35

... FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors EP3 ...

Page 36

... Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 36 Min. Max. 2.7 3.6 — — TBD 11.5 0 — 8.5 — 0.5 — Preliminary Unit Notes V Mhz Freescale Semiconductor, Inc. ...

Page 37

... FB_A[Y] FB2 FB_D[X] Address FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BEn FB_TA FB_TSIZ[1:0] Figure 11. FlexBus read timing diagram K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors FB3 FB5 Address FB4 Data AA=1 AA=0 FB4 FB5 AA=1 AA=0 TSIZ ...

Page 38

... FB_TA FB_TSIZ[1:0] Figure 12. FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 38 FB3 Address Data AA=1 AA=0 FB4 FB5 AA=1 AA=0 TSIZ Preliminary Freescale Semiconductor, Inc. ...

Page 39

... ADCK f ADC conversion ≤13 bit modes ADCK clock frequency f ADC conversion 16 bit modes ADCK clock frequency K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 24 and Table 25 Min. 1 Typ. 1.71 — -100 ...

Page 40

... For guidelines and examples of conversion rate calculation please download the ADC calculator tool http:// cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1 K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 40 Min. 1 Max. Typ. 18.484 — 818.330 37.037 — 361.402 = 1.0 MHz unless otherwise stated. Typical values are for ADCK Preliminary Unit Notes 6 Ksps 7 Ksps / AS Freescale Semiconductor, Inc. ...

Page 41

... Conversion Time The ADC calculator tool can be used to determine ADC conversion times for different ADC configurations: converters/ADC_CALCULATOR_CNV.zip?fpsp=1 TUE Total unadjusted • ≤13 bit modes error • <12 bit modes K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors SIMPLIFIED INPUT PIN EQUIVALENT Z CIRCUIT ADIN Pad leakage ...

Page 42

... LSB conversion ±0.5 clock <12MHz, Max hardware averaging (AVGE = %1, AVGS = %11) ±TBD Max 4 LSB averaging ±TBD ±TBD LSB ADIN V DDA ±TBD — 4 LSB ±0.5 5 TBD bits TBD bits TBD bits TBD bits dB 5 TBD dB TBD dB 5 — dB — dB Freescale Semiconductor, Inc. ...

Page 43

... Supply voltage Absolute DDA V PGA ref voltage REFPGA V Input voltage ADIN V Input Common CM Mode range K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors = REFH DDA REFL 1 Min. Typ. I × — TBD — ...

Page 44

... IN+ to IN- — — — Ω 5 — µs 6 causes drop AS 1 Max. Unit Notes TBD μ TBD μA 3 TBD R < 100Ω AS TBD TBD TBD TBD TBD TBD 4 kHz 40 kHz — DDA ±100mV 50Hz, VDDA 60Hz Freescale Semiconductor, Inc. ...

Page 45

... THD Total harmonic • Gain=1 distortion • Gain=64 SFDR Spurious free • Gain=1 dynamic range • Gain=64 K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. TBD TBD TBD TBD — 0.2 — ...

Page 46

... Typ. Max. Unit — 3.6 V — 200 μA — 20 μA — — Freescale Semiconductor, Inc. ...

Page 47

... Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level LSB = V /64 reference K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 1 — — ...

Page 48

... Peripheral operating requirements and behaviors 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0.1 0.4 0.7 Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011 1.3 1.6 1.9 2.2 Vin level (V) Preliminary HYSTCTR S etting 2.5 2.8 3.1 Freescale Semiconductor, Inc. ...

Page 49

... The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREFO small load capacitance (47 pF) can improve the bandwidth performance of the DAC K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 1 ...

Page 50

... TBD DACR ±8 LSB 2 ±1 LSB 3 ±1 LSB 4 ±0.8 %FSR 5 ±0.6 %FSR — μV/C — ppm of FSR/C TBD μV/yr 250 Ω V/μs — — -80 dB kHz — — Freescale Semiconductor, Inc. ...

Page 51

... Calculated by a best fit curve from V Figure 18. Typical INL error vs. digital code K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors +100 mV to VREF−100 mV SS Preliminary 51 ...

Page 52

... K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 52 Min. 1.71 — — — — — — — Table continues on the next page... Preliminary Typ. Max. Unit — 3 TBD μA 500 TBD μA ±3 TBD mV 10 — μV/C ±300 — pA TBD — pA ±300 — pA Freescale Semiconductor, Inc. ...

Page 53

... Table 32. TRIAMP full range operating requirements Symbol Description V Supply voltage DDA V Input voltage range IN C Output load capacitance L R Output resistance OUT K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — 0 — 500 — =100kHz) — 0 — ...

Page 54

... V -0.15 DD — ±0.5 — — 20 — — — 280 — — 100 — Preliminary Unit Notes μA μA mV μV MΩ pF MΩ V/μs V/μs MHz MHz deg nV/√Hz nV/√Hz Freescale Semiconductor, Inc. ...

Page 55

... Voltage reference electrical specifications Table 36. VREF full-range operating requirements Symbol Description V Supply voltage DDA T Temperature A C Output load capacitance L K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Max. 2.4 3.3 0.1 V -1.4 DDA 0 50 100 1500 Min ...

Page 56

... Typ. Max. Unit Notes 1.2 TBD V — TBD V — 1.202 V 0.5 — mV — See Figure 22 — TBD ppm/year — TBD µA — 1.1 mA — TBD V — 100 µs — TBD mV — TBD dB Max. Unit Notes 50 °C Max. Unit Notes TBD V Freescale Semiconductor, Inc. ...

Page 57

... VREGIN = 5.0 V and temperature=25C • Across operating voltage and temperature I Maximum load current — Run mode LOADrun I Maximum load current — Standby mode LOADstby K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. TBD 0 14.25 0.25 Min ...

Page 58

... Min. Max. 1.71 3.6 — 12 — BCLK (t / SCK SCK/ — SCK (t / — SCK — — 15 — 0 — Preliminary Unit Notes μF mΩ Load Unit Notes V 1 MHz Freescale Semiconductor, Inc. ...

Page 59

... DSPI_SS inactive to DSPI_SOUT not driven DSPI_SS DSPI_SCK (CPOL=0) DSPI_SOUT DS13 DSPI_SIN Figure 25. DSPI classic SPI timing — slave mode K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors DS1 DS2 DS8 Data Last data First data DS5 ...

Page 60

... BCLK (t /2) − / SCK SCK (t /2) − 2 — ns SCK (t /2) − 2 — ns SCK — 8.5 ns −2 — ns TBD — — ns DS4 Min. Max. Unit 2.7 3.6 V 12.5 MHz — ns BCLK (t /2) − SCK SCK Freescale Semiconductor, Inc. ...

Page 61

... This section provides the AC timings for the I modes (clocks input). All timings are given for non-inverted serial clock polarity (TCR[TSCKP RCR[RSCKP and a non-inverted frame sync (TCR[TFSI K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Description DS10 ...

Page 62

... Table continues on the next page... Preliminary Min. Max. Unit 2.7 3 SYS 45% 55% MCLK period — ns SYS 45% 55% BCLK period — -2.5 — ns — — — — S10 S8 Min. Max. Unit 2.7 3 — ns SYS Freescale Semiconductor, Inc. ...

Page 63

... Electrode oscillator frequency ELEmax C Internal reference capacitor REF V Oscillator delta voltage DELTA K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 2 S slave mode timing (continued) S11 S12 S15 S16 S18 2 S timing — slave modes Min ...

Page 64

... REFCHRG = 4 128, REF http://www.freescale.com and perform a keyword Then use this document number 98ASS23174W 98ASA10631D Preliminary Max. Unit Notes TBD μA 2 TBD μA 2 TBD % 3 TBD % 4 TBD % 5 — fF/count 6 — fF/count 7 16 bits 25 μs 8 — μA TBD μA Freescale Semiconductor, Inc. ...

Page 65

... VDDA VDDA • 16 VREFH VREFH VREFH • 17 VREFL VREFL VREFL • 18 VSSA VSSA VSSA • 19 ADC1_SE1 ADC1_SE1 ADC1_SE1 K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. NOTE ALT1 ALT2 ALT3 ALT4 Preliminary Pinout ALT5 ALT6 ALT7 EzPort 65 ...

Page 66

... K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 66 ALT1 ALT2 ALT3 ALT4 PTA0 UART0_CT FTM0_CH5 S_b PTA1 UART0_RX FTM0_CH6 PTA2 UART0_TX FTM0_CH7 PTA3 UART0_RT FTM0_CH0 S_b Preliminary ALT5 ALT6 ALT7 EzPort JTAG_TCL EZP_CLK K/ SWD_CLK JTAG_TDI EZP_DI JTAG_TDO/ EZP_DO TRACE_SW O JTAG_TMS/ SWD_DIO Freescale Semiconductor, Inc. ...

Page 67

... PTC1 / / ADC0_SE1 ADC0_SE1 5/ 5/ TSI0_CH14 TSI0_CH14 • 57 PTC2 / / ADC0_SE4 ADC0_SE4 b/ b/ K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTA4 FTM0_CH1 PTA18 FTM0_FLT2 FTM_CLKIN 0 PTA19 FTM1_FLT0 FTM_CLKIN 1 PTB0 I2C0_SCL FTM1_CH0 PTB1 I2C0_SDA FTM1_CH1 PTB2 ...

Page 68

... SPI0_SIN UART2_TX PTD4 SPI0_PCS1 UART0_RT FTM0_CH4 S_b Preliminary ALT5 ALT6 ALT7 EzPort FB_CLKOU T FB_AD11 CMP1_OUT CMP0_OUT FB_AD9 FB_AD8 FB_AD6 FTM2_FLT0 FB_AD5 FB_RW_b FB_CS5_b/ FB_TSIZ1/ FB_BE23_1 6_BLS15_8 _b FB_CS4_b/ FB_TSIZ0/ FB_BE31_2 4_BLS7_0_ b FB_ALE/ FB_CS1_b/ FB_TS_b FB_CS0_b FB_AD4 FB_AD3 FB_AD2 EWM_IN Freescale Semiconductor, Inc. ...

Page 69

... Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. The 81 MAPBGA ballmap assignments are currently being developed. K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 ...

Page 70

... The following table provides a revision history for this document. K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 70 Preliminary 60 VDD 59 VSS 58 PTC3 57 PTC2 56 PTC1 55 PTC0 54 PTB19 53 PTB18 52 PTB17 51 PTB16 50 VDD 49 VSS 48 PTB11 47 PTB10 46 PTB3 45 PTB2 44 PTB1 43 PTB0 42 RESET_b 41 PTA19 Freescale Semiconductor, Inc. ...

Page 71

... Rev. No. Date 2 3/2011 3 3/2011 4 3/2011 K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Table 49. Revision History Substantial Changes Initial public revision Added sections that were inadvertently removed in previous revision Reworded I footnote in "Voltage and Current Operating Requirements" IC table. Added paragraph to "Peripheral operating requirements and behaviors" ...

Page 72

... For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program http://www.freescale.com/epp. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010–2011 Freescale Semiconductor, Inc. ...

Related keywords