at24cs128 ATMEL Corporation, at24cs128 Datasheet
at24cs128
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at24cs128 Summary of contents
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... JEDEC PDIP and 8-Pin JEDEC and EIAJ SOIC Packages Description The AT24CS128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device’s cascadable feature allows devices to share a common 2-wire bus ...
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... If left unconnected internally pulled down to GND. Switching prior to a write operation cre- CC ates a software write protect function. Memory Organization AT24CS128/256, 128K/256K SERIAL EEPROM: The 128K/256K is internally organized as 256/512 pages of 64- bytes each. Random word addressing requires a 14/15-bit data word address. ...
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Pin Capacitance Applicable over recommended operating range from T Symbol Test Condition C Input/Output Capacitance (SDA) I/O C Input Capacitance (A IN Note: This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range ...
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... EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The AT24CS128/256 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations ...
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Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O) Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O) SCL SDA 8th BIT WORD n Note: 1. The write cycle time t WR cycle. ACK STOP CONDITION is the time ...
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... Data Validity Start and Stop Definition Output Acknowledge AT24CS128/256 6 ...
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... The OTP feature provides the user with a 2048-bit (256 x 8) security section, which once programmed and enabled, becomes read-only and data cannot be changed or over- written. The OTP section is located in the upper 2K section of the memory array in the AT24CS128/256. If not enabled, the OTP section will function as part of the normal memory array. . ...
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... Figure 1. Device Address Figure 2. Byte Write Figure 3. Page Write (* = DON’T CARE bit) († = DON’T CARE bit for the 128K) AT24CS128/256 8 SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge ...
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Figure 4. Current Address Read Figure 5. Random Read (* = DON’T CARE bit) († = DON’T CARE bit for the 128K) Figure 6. Sequential Read 9 ...
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... AT24CS128 Ordering Information t (max) I (max) I (max (ms 3000 5.0 3000 5.0 10 1500 0.5 1500 0.5 20 800 0.2 800 0.2 8P3 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8S2 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Blank Standard Operation (4 ...
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AT24CS256 Ordering Information t (max) I (max (ms 3000 3000 10 1500 1500 20 800 800 8P3 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-Lead, 0.200" Wide, Plastic Gull ...
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Packaging Information 8P3, 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 BA .400 (10.16) .355 (9.02) PIN 1 .300 (7.62) REF .210 (5.33) MAX .100 (2.54) BSC SEATING PLANE .150 (3.81) .115 ...