at24cs128 ATMEL Corporation, at24cs128 Datasheet - Page 4

• Manufacturer Part Number: at24cs128
• Description: 2-wire Serial Eeproms With Permanent Software Write Protect
• Manufacturer: ATMEL Corporation

AC Characteristics
Applicable over recommended operating range from T
erwise noted). Test conditions are listed in Note 2.
Notes:
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as defined
below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
4
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Endurance
SCL
LOW
HIGH
AA
BUF
HD.STA
SU.STA
HD.DAT
SU.DAT
R
F
SU.STO
DH
WR
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
(1)
R
Input pulse voltages: 0.3V
Input rise and fall times: 50ns
Input and output timing reference voltages: 0.5V
L
(connects to V
AT24CS128/256
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Time the bus must be free before a new
transmission can start
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time
Inputs Fall Time
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Page Mode
CC
): 1.3K
(1)
CC
(1)
to 0.7V
(2.7V, 5V), 10K (1.8V)
(1)
CC
A
CC
= -40 C to +85 C, V
100K
100
Min
1.3
1.0
0.1
1.2
0.6
0.6
0.6
ACKNOWLEDGE: All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24CS128/256 features a low
power standby mode which is enabled: a) upon power-up
and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps: (a) Clock up to 9 cycles, (b) look for SDA
high in each cycle while SCL is high and then (c) create a
start condition as SDA is high.
50
0
1.8-volt
Max
400
300
0.9
0.3
20
CC
= +1.8V to +5.5V, CL = 100 pF (unless oth-
100K
0.05
0.25
0.25
0.25
100
Min
0.6
0.4
0.5
50
0
2.7-volt
1000
0.55
Max
100
0.3
10
100K
0.05
0.25
0.25
0.25
100
Min
0.6
0.4
0.5
50
0
5.0-volt
1000
Max
0.55
100
0.3
10
Cycles
Units
Write
kHz
ms
ns
ns
ns
s
s
s
s
s
s
s
s
s