psd813f1a STMicroelectronics, psd813f1a Datasheet - Page 15

• Manufacturer Part Number: psd813f1a
• Description: Flash In-system Programmable Isp Peripherals For 8-bit Mcus, 5 V
• Manufacturer: STMicroelectronics

JTAG Port
In-System
through the JTAG pins on Port C. This serial inter-
face allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port C. Table
JTAG signals pin assignments.
In-System Programming (ISP)
Using the JTAG signals on Port C, the entire PSD
device can be programmed or erased without the
use of the microcontroller. The main Flash memo-
ry can also be programmed in-system by the mi-
crocontroller
algorithms out of the EEPROM or SRAM. The EE-
PROM can be programmed the same way by exe-
cuting out of the main Flash memory. The PLD
logic or other PSD configuration can be pro-
grammed through the JTAG port or a device pro-
grammer. Table
methods can program different functional blocks
of the PSD.
Page Register
The 8-bit Page Register expands the address
range of the microcontroller by up to 256 times.
The paged address can be used as part of the ad-
dress space to access external memory and pe-
ripherals, or internal memory and I/O. The Page
Register can also be used to change the address
mapping of blocks of Flash memory into different
memory spaces for in-circuit programming.
Table 4. Methods of Programming Different Functional Blocks of the PSD
Main Flash Memory
EEPROM Memory
PLD Array (DPLD and CPLD)
PSD Configuration
Optional OTP Row
Programming
Functional Block
executing
4
indicates which programming
can
the
be
3
programming
indicates the
performed
Yes
Yes
Yes
Yes
No
JTAG Programming
Power Management Unit (PMU)
The Power Management Unit (PMU) in the PSD
gives the user control of the power consumption
on selected functional blocks based on system re-
quirements. The PMU includes an Automatic Pow-
er Down unit (APD) that will turn off device
functions due to microcontroller inactivity. The
APD unit has a Power Down Mode that helps re-
duce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The turbo bit in the PMMR0 reg-
ister can be turned off and the CPLD will latch its
outputs and go to sleep until the next transition on
its inputs.
Additionally, bits in the PMMR2 register can be set
by the MCU to block signals from entering the
CPLD to reduce power consumption. Please see
the
MANAGEMENT, page 64
Table 3. JTAG SIgnals on Port C
PC0
PC1
PC3
PC4
PC5
PC6
Port C Pins
Yes
Yes
Yes
Yes
Yes
Device Programmer
section
TMS
TCK
TSTAT
TERR
TDI
TDO
entitled
for more details.
JTAG Signal
Yes
Yes
No
No
Yes
In-System Parallel
Programming
PSD813F1A
POWER
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