lt3692a Linear Technology Corporation, lt3692a Datasheet - Page 10

• Manufacturer Part Number: lt3692a
• Description: Monolithic Dual Tracking 3.5a Step-down Switching Regulator
• Manufacturer: Linear Technology Corporation

LT3692A
BLOCK DIAGRAM
The LT3692A is a dual channel, constant frequency, current
mode buck converter with internal 3.8A switches. Each
channel can be independently controlled with the exception
that V
lockout threshold to power the common internal regulator,
oscillator and thermometer circuitry.
If the SHDN1 pin is taken below its 1.32V threshold the
LT3692A will be placed in a low quiescent current mode. In
this mode the LT3692A typically draws 6μA from V
<1μA from V
internal bias circuits turn on generating an internal regulated
voltage, 0.806V
references, and a POR signal which sets the soft-start latch.
Once the internal reference reaches its regulation point,
the internal oscillator will start generating a master clock
signal for the two regulators at a frequency determined by
the voltage present at the RT/SYNC pin. The channel 1 clock
10
R
R
LIM
DIV
R3
V
IN1
IN1
must be above the typically 2.8V undervoltage
SHDN1
SS1
V
ILIM1
RT/SYNC
DIV
IN2
C1
. When the SHDN pin is driven above 1.32V, the
FB
, 12μA RT/SYNC, DIV and ILIM current
2.5V
2.5V
2.5V
2.5V
12μA
12μA
12μA
12μA
90mV
COMPENSATION
OSCILLATOR
1.32V
AND AGC
SLOPE
–
+
+
–
CLK1
MASTER CLOCK
CLK2 TO CHANNEL 2
Figure 1. LT3692A Block Diagram
S
R
PRE
IN1
Q
THERMAL
SHUTDOWN
and
+
–
39V
is then divided by 1, 2, 4 or 8 depending on the voltage
present at the DIV pin. Channel 2’s clock runs at the master
clock frequency with a 180° phase shift from channel 1.
Alternatively, if a synchronization signal is detected by
the LT3692A the RT/SYNC pin, the master clock will be
generated at the incoming frequency on the rising edge
of the synchronization pulse with channel 1 in phase with
the synchronization signal. Frequency division and phase
remains the same as the internally generated master clock.
In addition, the internal slope compensation will be au-
tomatically adjusted to prevent subharmonic oscillation
during synchronization. In either mode of oscillator op-
eration, a square wave with the master clock frequency,
synchronized to channel 1 is present at the CLKOUT pin.
The two regulators are constant frequency, current mode
step-down converters. Current mode regulators are con-
–
+
2.8V
V
IN1
+
–
S
R
PRE
+
+
–
Q
0.806V
REFERENCES
REGULATOR
INTERNAL
AND
ENHANCEMENT
CHANNEL 1
CIRCUITRY
DROPOUT
DRIVER
0.72V
+
–
+
–
2.5V
CLKOUT
CMPO1
CMPI1
V
BST1
IND1
SW1
OUT1
GND
V
FB1
IN1
3692a F01
T
J
R1
R2
3692af