lt3692a Linear Technology Corporation, lt3692a Datasheet - Page 11

• Manufacturer Part Number: lt3692a
• Description: Monolithic Dual Tracking 3.5a Step-down Switching Regulator
• Manufacturer: Linear Technology Corporation

BLOCK DIAGRAM
trolled by an internal clock and two feedback loops that
control the duty cycle of the power switch. In addition to
the normal error amplifier, there is a current sense amplifier
that monitors switch current on a cycle-by-cycle basis.
This technique means that the error amplifier commands
current to be delivered to the output rather than voltage.
A voltage fed system will have low phase shift up to the
resonant frequency of the inductor and output capacitor,
then an abrupt 180° shift will occur. The current fed sys-
tem will have 90° phase shift at a much lower frequency,
but will not have the additional 90° shift until well beyond
the LC resonant frequency. This makes it much easier to
frequency compensate the feedback loop and also gives
much quicker transient response.
The Block Diagram in Figure 1 shows only one of the
switching regulators whose operation will be discussed
below. The additional regulator will operate in a similar
manner with the exception that its clock will be 180° out
of phase with the other regulator.
When, during power-up, an internal POR signal sets the
soft-start latch, both SS pins will be discharged to ground
to ensure proper start-up operation. When the SS pin volt-
age drops below 90mV, the V
switching and the soft-start latch is reset. Once the latch
is reset the soft-start capacitor starts to charge with a
typical value of 12μA.
As the voltage rises above 115mV on the SS pin, the V
pin will be driven high by the error amplifier. When the
voltage on the V
the driver flip-flop, which turns on the internal power NPN
switch. This causes current from V
switch, inductor and internal sense resistor to increase.
When the voltage drop across the internal sense resistor
exceeds a predetermined level set by the voltage on the
V
is turned off. Once the switch is turned off the inductor
will drive the voltage at the SW pin low until the external
Schottky diode starts to conduct, decreasing the current
in the inductor. The cycle is repeated with the start of each
clock cycle. However, if the internal sense resistor voltage
exceeds the predetermined level at the start of a clock cycle,
the flip-flop will not be set resulting in a further decrease
in inductor current. Since the output current is controlled
C
pin, the flip-flop is reset and the internal NPN switch
C
pin exceeds 0.9V, the clock set-pulse sets
C
pin is driven low disabling
IN
, through the NPN
C
by the V
error amplifier continually adjusting the V
The error amplifier is a transconductance amplifier that
compares the FB voltage to the lowest voltage present at
either the SS pin or an internal 806mV reference. Compen-
sation of the loop is easily achieved with a simple capacitor
or series resistor/capacitor from the V
The regulators’ maximum output current occurs when
the V
error amplifier. The value of the typical maximum switch
current can be programmed from 4.8A to 2A by placing
a resistor from the ILIM pin to ground.
Since the SS pin is driven by a constant current source, a
single capacitor on the soft-start pin will generate controlled
linear ramp on the output voltage.
If the current demanded by the output exceeds the maxi-
mum current dictated by the V
will be discharged, lowering the regulation point until the
output voltage can be supported by the maximum current.
Once the overload condition is removed, the regulator will
soft-start from the overload regulation point.
Shutdown control, V
will set the soft-start latch, resulting in a complete soft-
start sequence.
The switch driver operates from either the V
age. An external diode and capacitor are used to generate
a drive voltage higher than V
and maintain high efficiency. If the BST capacitor voltage
is sufficient, the switch is allowed to operate to 100% duty
cycle. If the boost capacitor discharges towards a level
insufficient to drive the output NPN, a BST pin compara-
tor forces a minimum cycle off time, allowing the boost
capacitor to recharge.
A comparator with a threshold of 720mV and 60mV of
hysteresis is provided for detecting error conditions. The
CMPO output is an open-collector NPN that is off when
the CMPI pin is above the threshold allowing a resistor
to pull the CMPO pin to a desired voltage.
The voltage present at the T
temperature of the LT3692A. The T
die temperature of 25°C and will have a slope of 10mV/°C.
C
pin is driven to its maximum clamp value by the
C
voltage, output regulation is achieved by the
IN
overvoltage, or thermal shutdown
J
pin is proportional to the junction
IN
to saturate the output NPN
C
J
pin clamp, the SS pin
pin will be 250mV for a
C
LT3692A
pin to ground.
C
IN
pin voltage.
or BST volt-
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3692af