hip1011d Intersil Corporation, hip1011d Datasheet - Page 8

• Manufacturer Part Number: hip1011d
• Description: Dual Plug Controller
• Manufacturer: Intersil Corporation

Time Delay to Latch-Off
Time delay to latch-off allows for a predetermined delay from
an OC or UV event to the simultaneous latch-off of all four
supply switches of the affected slot by the HIP1011D. This
delay period is set by the capacitance value to ground from
the FLTN pins for each slot. This capacitance value tailors
the FLTN signal going low ramp rate. This provides a delay
to the fault signal latch-off threshold voltage, FLTN, Vth. By
increasing this time, the HIP1011D delays immediate latch-
off of the bus supply switches, thus ignoring transient OC
and UV conditions. See additional information in the “Using
the HIP1011DEVAL1 Platform” section of this data sheet.
Caution: The primary purpose of a protection device such
as the HIP1011D is to quickly isolate a faulted card from the
voltage bus. Delaying the time to latch-off works against this
primary concern so care must be taken when using this
feature. Ensure adequate sizing of external FETs to carry
additional current during time out period. Understand that
voltage bus disruptions must be minimized for the time delay
period in the event of a crow bar failure.
Devices using an unadjustable preset delay to latch-off time
present the user with the inability to eliminate these
concerns increasing cost and the chance of additional ripple
through failures.
HIP1011D Soft Start and Turn-Off Considerations
The HIP1011D does allow the user to select the rate of ramp
up on the voltage supplies. This start-up ramp minimizes in-
rush current at start-up while the on card bulk capacitors
charge. The ramp is created by placing capacitors on
M12VG to M12VO, 12VG to 12VO and 3V5VG to ground.
These capacitors are each charged up by a nominal 25 A
current during turn on. The same value for all gate timing
capacitors is recommended. A recommended minimum
value of 0.033 F as a smaller value may cause overcurrent
faults at power up. This recommendation results in a nominal
gate voltage ramp rate of 0.76V/ms. The gate capacitors
must be discharged when a fault is detected to turn off the
power FETs. Thus, larger caps slow the response time. If the
gate capacitors are too large the HIP1011D may not be able
to adequately protect the bus or the power FETs. The
HIP1011D has internal discharge FETs to discharge the
load when disabled. Upon turn-off these internal switches on
each output discharge the load capacitance pulling the
output to gnd. These switches are also on when PWRON is
low thus an open slot is held at the gnd level.
+3.3V I
+5.0V I
+12V I
-12V I
SUPPLY
OC
OC
OC
OC
((100 A x R
((100 A x R
(100 A x R
(100 A x R
HOW TO DETERMINE NOMINAL ( 10%) I
OCSET
OCSET
OCSET
OCSET
TABLE 1.
FOR EACH SUPPLY
)/0.8
)/3.3
)/11.5)/R
)/14.5)/R
8
RSENSE
RSENSE
OC
HIP1011D
Decoupling Precautions and Recommendations
For the HIP1011D proper decoupling is a particular concern
during the normal switching operation and especially during
a card crowbar failure. If a card experiences a crow bar short
to ground, the supply to the other card will experience
transients until the faulted card is isolated from the bus. In
addition the common IC nodes between the two sides can
fluctuate unpredictably resulting in a false latch-off of the
second slot. Additionally to the mother board bulk
capacitance, it is recommended that 10 F capacitors be
placed on both the +12V and -12V lines of the HIP1011D as
close to the chip as possible.
Recommended PCB Layout Design Best Practices
To ensure accurate current sensing, PCB traces that
connect each of the current sense resistors to the HIP1011D
must not carry any load current. This can be accomplished
by two dedicated PCB kelvin traces directly from the sense
resistors to the HIP1011D, see examples of correct and
incorrect layouts below in Figure 3. To reduce parasitic
inductance and resistance effects, maximize the width of the
high-current PCB traces.
VS AND VISEN
TO HIP1011D
CORRECT
FIGURE 3. SENSE RESISTOR PCB LAYOUT
SENSE RESISTOR
CURRENT
VS AND VISEN
TO HIP1011D
INCORRECT