tza3012ahw NXP Semiconductors, tza3012ahw Datasheet - Page 15

• Manufacturer Part Number: tza3012ahw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-ratetm Fibre Optic Receiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Prescaler outputs
The frequency of prescaler outputs PRSCLO and
PRSCLOQ is the VCO frequency divided by a ratio of N.K.
If the synthesizer is in-lock, the frequency of the prescaler
output is equal to the reference frequency at CREF and
CREFQ divided by R which also corresponds to the
recovered data rate. This provides an accurate reference
that can be used by other phase locked loops in the
application. If required, the polarity of the prescaler outputs
can be inverted by setting bit PRSCLOINV in I
register IOCNF0 (address CBH) to logic 1. If no prescaler
information is required, its output can be disabled by
setting bit PRSCLOEN in the same register to logic 0.
In addition, the prescaler output can be set for type of
output, termination mode and signal amplitude. These
parameter settings also apply to the parallel output
clock POCLK and POCLKQ and parity error
output PARERR and PARERRQ. For programming
details, These parameter settings also apply to the parallel
demultiplexer outputs. For programming details;
see Section “Configuring the parallel interface”.
Programming the FWD
The default window for frequency acquisition is 1000 ppm
around the desired bit rate. The size of window determines
the amount of variation in the frequency of the applied
reference clock, and VCO, that is tolerated by the FWD.
The window size can be set to other predefined values
between 250 and 2000 ppm by bits WINDOWSIZE in
I
An additional feature allows the size of the frequency
acquisition window to be set to 0 ppm, which effectively
removes the ‘dead zone’ from the FWD, converting it to a
classical PLL. The VCO will then be directly phase-locked
to the reference signal instead of the incoming bit stream.
This is implemented by either applying a LOW level to
pin WINSIZE, or by setting bit WINSIZE to logic 0 and
bit I2CWINSIZE to logic 1 in I
see Table 10.
Table 10 Truth table for pin WINSIZE
2003 May 21
2
C-bus register DCRCNF (address B6H).
30 Mbits/s up to 3.2 Gbits/s
A-rate
WINSIZE
HIGH
LOW
fibre optic receiver
2
C-bus register DCRCNF;
WINDOW SIZE (ppm)
1000
0
2
C-bus
15
Accurate clock generation during loss of signal
During a loss of signal, there is no data present for clock
recovery to use. A frequency acquisition window size of
zero will make the recovered clock frequency equal to the
reference frequency, including its tolerance.
Setting bit AUTOWIN in I
the window size dependent on the LOS status of the active
limiter channel. If the optical input signal is lost, the FWD
automatically selects the 0 ppm window size, so that the
VCO is directly phase-locked to the reference signal.
This ensures that the output clock signal remains stable
during loss of signal, and automatically reverts to normal
DCR operation when the input signal returns.
Note that the accuracy of the reference frequency must be
better than 20 ppm for the application to comply with ITU-T
recommendations.
INWINDOW signal
The status of the FWD circuit is indicated by the level on
pin INWINDOW. A HIGH level indicates that the VCO is
within the defined frequency acquisition window size, and
a LOW level indicates that the VCO is outside the defined
window size. The status of the FWD circuit is also
indicated by bit INWINDOW in I
registers INTERRUPT and STATUS.
Jitter performance
The clock synthesizer is optimized for minimum jitter
generation. For all SDH/SONET bit rates, the generated
jitter complies with ITU-T standard G.958 using a pure
reference clock. To ensure negligible loss of performance
when a reference clock is used, the reference signal
should have a single sideband phase noise of better than
carrier. If reference divider R is used, this negative value is
allowed to increase at approximately 20
Demultiplexer
The demultiplexer converts the serial input bit stream to
parallel formats of 1:16, 1:10, 1:8, and 1:4. The output data
is available on a scalable bus, of which the output driver
type can be either LVPECL or CML. In addition to the
deserializing function, the demultiplexer comprises a parity
calculator and a frame header detection circuit.
A calculated parity of EVEN is output at pins PARITY and
PARITYQ. A detected frame header pattern in the data
stream results in a 1 clock cycle wide pulse on outputs FP
and FPQ.
140 dBc/Hz, at frequencies of more than 12 kHz from the
2
C-bus register DCRCNF makes
2
C-bus
TZA3012AHW
Product specification
log (R).