tza3012ahw NXP Semiconductors, tza3012ahw Datasheet - Page 19

• Manufacturer Part Number: tza3012ahw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-ratetm Fibre Optic Receiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Parity generation
Outputs PARITY and PARITYQ provide the even parity of
the byte/word that is currently available on the parallel bus.
Odd parity can be output by setting bit PARINV to logic 1
in I
output is required, and/or to reduce output power, set
bit PAREN, in the same register, to logic 0.
Configuring the parallel interface
There are several options for configuring the parallel
interface which comprises the parallel data bus and
associated outputs. The options for parallel data
output D00 to D15 and D00Q to D15Q, parallel clock
output POCLK and POCLKQ, parity output PARITY and
PARITYQ, frame pulse output FP and FPQ, and prescaler
output PRSCLO and PRSCLOQ are: output driver type,
termination mode, output amplitude, signal polarity, and
selective enabling or disabling. The parallel data bus pin
designations can also be reversed and/or muted. These
options are set in I
(address C8H) and IOCNF2 (address C9H), IOCNF0
(address CBH) and DMXCNF (address A8H).
I
the CML or LVPECL output driver. The default is LVPECL.
Bit MFOUTTERM sets the output termination mode to
either standard LVPECL or floating termination, or in CML
mode, to either DC or AC-coupled. In all cases, bits MFS
adjust the amplitude. The default output amplitude is
800 mV (p-p) single-ended.
In I
disables the parallel interface output driver. This is not the
same effect as setting bit DMXMUTE in I
register DMXCNF (address A8H), which forces the
outputs to a logic 0 state. Setting bit PDINV to logic 1 in
I
polarity of the parallel data. Setting bit POCLKINV to
logic 1 in the same register inverts the clock output so that
the clock edge is shifted by half a clock cycle, changing the
rising edge to a falling edge. This function can be used to
resolve a parallel data bus timing problem. The parallel
bus clock is disabled by setting bit POCLKEN to logic 0 in
the same register. Control bits in the same register and in
register IOCNF0 (address CBH) also apply the same
options to the parity, frame pulse and prescaler outputs.
2003 May 21
2
2
C-bus register IOCNF3, bit MFOUTMODE selects either
C-bus register IOCNF2 (address C9H) inverts the
30 Mbits/s up to 3.2 Gbits/s
A-rate
2
2
C-bus register IOCNF2 (address C9H). If no parity
C-bus register IOCNF2, setting bit PDEN to logic 0
fibre optic receiver
2
C-bus registers IOCNF3
2
C-bus
19
Loop mode I/Os
In line loopback mode, the internal data and clock routing
switch routes the received serial data and recovered clock
to outputs DOUT, DOUTQ COUT and COUTQ instead of
to the demultiplexer. Line loopback mode is activated by a
LOW level on pin ENLOUTQ. Line loopback mode is also
selected by setting bit ENLOOPOUT and
bit I2CLOOPMODE in I
(address B0H).
In diagnostic loopback mode, the demultiplexer selects the
serial data and clock signals at loop mode input
pins DLOOP, DLOOPQ and CLOOP, CLOOPQ instead of
from the DCR. Diagnostic loopback mode is activated by a
LOW level on pin ENLINQ. Diagnostic loopback mode is
also selected by setting bit ENLOOPIN and
bit I2CLOOPMODE in I
(address B0H).
Configuring the RF I/Os
The polarity of specific RF serial data and clock I/O signals
can be inverted using I
(address CAH).
To allow easier connection to other ICs, the pin
designations for input data can be exchanged with the pin
designations for input clock. The pin designations for
output data and output clock can also be exchanged.
The default pin designations for Loop mode input data and
clock are exchanged by setting bit CDINSWAP in I
register IOCNF1 so that signals at pins CLOOP and
CLOOPQ are treated as data and signals at pins DLOOP
and DLOOPQ are treated as clock.
The default pin designations for Loop mode output data
and clock are exchanged by setting bit CDOUTSWAP in
I
COUTQ are treated as data and signals at pins DOUT and
DOUTQ are treated as clock.
The amplitude of the RF serial output signals in CML drive
mode, is adjustable (in 16 steps) between 60 mV (p-p) and
1000 mV (p-p), single-ended, controlled by bits RFS
and RFSWING in I
(address CBH). The default amplitude is 80 mV (p-p),
single-ended. The RF serial outputs are AC-coupled.
2
C-bus register IOCNF1 so that signals at pins COUT and
2
C-bus register IOCNF0
2
2
2
C-bus register IOCNF1
C-bus register DIVCNF
C-bus register DIVCNF
TZA3012AHW
Product specification
2
C-bus