W83194R-37/-58 Winbond Electronics Corp America, W83194R-37/-58 Datasheet
W83194R-37/-58
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W83194R-37/-58 Summary of contents
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... Winbond for any damages resulting from such improper use or sales 100MHZ AGP CLOCK FOR VIA CHIPSET W83194R-37/58 Data Sheet Revision History Version On Web n.a. All of the versions before 0.50 are for internal use. 1.0 Change version and version on web site to 1.0 W83194R-37/-58 Main Contents Publication Release Date:Sep 1998 Revision 1.0 ...
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... EMI. The W83194R-37/-58 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± ...
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BLOCK DIAGRAM X1 X2 *FS(0:2) 3 *MODE CPU3.3#_2.5 *SD_SEL# CPU_STOP# PCI_STOP# *SDATA *SCLK 4.0 PIN CONFIGURATION Vdd * REF0/CPU3.3#_2.5 Vss Xin Xout Vddq3 PCICLK_F/*FS1 PCICLK0/*FS2 Vss PCICLK1 PCICLK2 PCICLK3 PCICLK4 Vddq3 AGP0 Vss CPU_STOP#/SDRAM11 PCI_STOP#/SDRAM10 Vddq3 SDRAM 9 SDRAM ...
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PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250kΩ pull-up 5.1 Crystal I/O SYMBOL PIN Xin 4 Xout 5 5.2 CPU, SDRAM, PCI Clock Outputs SYMBOL PIN CPUCLK ...
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CPU, SDRAM, PCI Clock Outputs, continued SYMBOL PIN PCICLK 0 / *FS2 8 PCICLK [ 1:4 ] 10,11,12, Control Interface SYMBOL PIN SDATA 23 SDCLK 24 5.4 Fixed Frequency Outputs SYMBOL PIN REF0 / CPU3.3#_2.5 ...
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... FS2 FS1 FS0 CPU(MHz 100 6.2 W83194R-58 Frequency Selection Table FS2 FS1 FS0 CPU(MHz 112 66 124 133 83 95. 100 ...
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... The W83194R-37/-58 may be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop ...
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... Ack Byte count Byte 1 Ack Description 0 = ±1.5% Spread Spectrum Modulation 1 = ±0.5% Spread Spectrum Modulation(W83194R-37 ±0.25% Spread Spectrum Modulation 1 = ±0.5% Spread Spectrum Modulation(W83194R-58) SSEL2 ( Frequency table selection by software via I SSEL1 ( Frequency table selection by software via I SSEL0 ( Frequency table selection by software via Selection by hardware ...
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... W83194R-37 Frequency table selection by software via I SSEL2 SSEL1 SSEL0 CPU(MHz W83194R-58 Frequency table selection by software via I SSEL2 SSEL1 SSEL0 Register0 Bit2 SSEL3 ...
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FUNCTION TABLE Function Description CPU Hi-Z Tri-State Normal see table 8.3.2 Register 1 : CPU , 48/24 MHz Clock Register (1 = Active Inactive) Bit @PowerUp Pin ...
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Register 4: Additional SDRAM Clock Register (1 = Active Inactive) Bit @PowerUp Pin ...
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SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. ...
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DC CHARACTERISTICS ± Vddq2 = Vdd = Vddq3 = 3.3V Parameter Symbol Input Low Voltage V Input High Voltage V Input Low Current Input High Current I Output Low Voltage Output High Voltage ...
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BUFFER CHARACTERISTICS 9.4.1 TYPE 1 BUFFER FOR CPU (0:3) Parameter Symbol Pull-Up Current Min I OH(min) Pull-Up Current Max I OH(max) Pull-Down Current Min I OL(min) Pull-Down Current Max I OL(max) Rise/Fall Time Min T RF(min) Between 0.4 V ...
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TYPE 3 BUFFER FOR REF(0:1), 24MHZ, 48MHZ Parameter Symbol Pull-Up Current Min I OH(min) Pull-Up Current Max I OH(max) Pull-Down Current Min I OL(min) Pull-Down Current Max I OL(max) Rise/Fall Time Min T RF(min) Between 0.8 V and 2.0 ...
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POWER MANAGEMENT TIMING 10.1 CPU_STOP# Timing Diagram CPUCLK (Internal) PCICLK (Internal) PCICLK_F CPU_STOP# CPUCLK[0:3] SDRAM For synchronous Chipset, CPU_STOP# pin is a synchronous “ active low ” input pin used to stop the CPU clocks for low power operation. ...
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OPERATION OF DUAL FUCTION PINS Pins 25, and 26 are dual function pins and are used for selecting different functions in this device (see Pin description). During power up, these pins are in input mode (see ...
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Vdd Ω 10k Device Pin Ω 10k Ground Programming Header Vdd Pad 10kΩ Device Pin - 18 - Series Terminating Clock Resistor Trace EMI Reducing Cap Optional Ground Ground Pad Series Terminating Clock Resistor Trace EMI Reducing Cap Optional Ground ...
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... Ferrite Bead (FB) are recommended to further reduce the power supply noise. 5.The power supply race to the Vdd pins must be thick enough so that voltage drops across the trace resistance is negligible. FB1 Vdd Vdd Plane (3.3V) C1 C31 C32 C33 C34 - 19 - W83194R-37/-58 Vdd2 Plane ...
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... W83194R-37 28051234 814GBB W83194R-58 28051234 814GBB 1st line: Winbond logo and the type number: W83194R-37/-58 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 814: packages made in '98, week 14 G: assembly house ID ...
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PACKAGE DRAWING AND DIMENSIONS Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Taipei Office 9F, No. 480, Rueiguang Road, Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579 Please note ...