lm9627 National Semiconductor Corporation, lm9627 Datasheet - Page 19

• Manufacturer Part Number: lm9627
• Description: Color Cmos Image Sensor Vga 30 Fps
• Manufacturer: National Semiconductor Corporation

Functional Description
13.0 SERIAL BUS
The serial bus interface consists of the sda (serial data), sclk
(serial clock) and sadr (device address select) pins. The
LM9627 can operate only as a slave.
The sclk pin is an input, it only and controls the serial interface,
all other clock functions within LM9627 use the master clock pin,
mclk.
13.1
The serial bus will recognize a logic 1 to logic 0 transition on the
sda pin while the sclk pin is at logic 1 as the start condition. A
logic 0 to logic 1 transition on the sda pin while the sclk pin is at
logic 1 is interrupted as the stop condition as shown in Figure
27.
13.2
The serial bus Device Address of the LM9627 is set to 1010101
when sadr is tied low and 0110011 when sadr is tied high. The
value for sadr is set at power up.
13.3
The LM9627 will hold the value of the sda pin to a logic 0 during
the logic 1 state of the Acknowledge clock pulse on sclk as
shown in Figure 28.
Confidential
sda
sclk
sda
sclk
from master
sda
sclk
sda
from sensor
start condition
Start/Stop Conditions
Device Address
Acknowledgment
START
S
S
S
START
S
Figure 27. Start/Stop Conditions
Device
Address
Figure 28. Acknowledge
MSB
1
MSB
1
2
2
W
S
(continued)
A
7
Address
Device
7
stop condition
Figure 31. Serial Bus Write Operation
Figure 32. Serial Bus Read Operation
Register
Address
Figure 30. Serial Bus Byte Format
8
Clock pulse
P
for ACK
W
byte complete
8
9
from receiver
A
ack signal
ACK
ACK
ACK
9
A
Register
Address
19
clock line
held low
S
13.4
The master must ensure that data is stable during the logic 1
state of the sclk pin. All transitions on the sda pin can only occur
when the logic level on the sclk pin is “0” as shown in Figure 29.
13.5
Every byte consists of 8 bits. Each byte transferred on the bus
must be followed by an Acknowledge. The most significant bit of
the byte is should always be transmitted first. See Figure 30.
13.6
A write operation is initiated by the master with a Start Condition
followed by the sensor’s Device Address and Write bit. When
the master receives an Acknowledge from the sensor it can
transmit 8 bit internal register address. The sensor will respond
with a second Acknowledge signaling the master to transmit 8
write data bits. A third Acknowledge is issued by the sensor
when the data has been successfully received.
The write operation is completed when the master asserts a
Stop Condition or a second Start Condition. See Figure 31.
13.7
A read operation is initiated by the master with a Start Condition
followed by the sensor’s Device Address and Write bit. When
the master receives an Acknowledge from the sensor it can
transmit the internal Register Address byte. The sensor will
respond with a second Acknowledge. The master must then
issue a new Start Condition followed by the sensor’s Device
Address and read bit. The sensor will respond with an Acknowl-
edged followed by the Read Data byte.
The read operation is completed when the master asserts a Not
Acknowledge followed by Stop Condition or a second Start Con-
dition. See Figure 32.
sda
sclk
Address
A
Device
Data Valid
Byte Format
Write Operation
Read Operation
1
Data
Byte
data valid
data line
stable;
2
Figure 29. Data Validity
A
R
P
A
change
of data
allowed
8
Data
Byte
ACK
bold sensor action
9
data valid
bold sensor action
data line
from receiver
stable;
ack signal
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A
P
P