lm9627 National Semiconductor Corporation, lm9627 Datasheet - Page 26

• Manufacturer Part Number: lm9627
• Description: Color Cmos Image Sensor Vga 30 Fps
• Manufacturer: National Semiconductor Corporation

Register Set
Register Name Hclk Generator Register
Address
Mnemonic
Type
Reset Value
Register Name Digital Video Mode 0
Address
Mnemonic
Type
Reset Value
Confidential
7:0
7:6
5:4
3:0
Bit
Bit
HclkGen
PixDataSel
PixDataMsb
Bit Symbol
Bit Symbol
05 Hex
VCLKGEN
Read/Write
04 Hex.
06 Hex
VMODE0
Read/Write
00 Hex
(continued)
Use to program the number of
active bits on the digital video bus
d[11:0], starting from the MSB
(d[11]). Inactive bits are tri-stated.:
Use to program the routing of the
MSB output of the internal video
A/D to a bit on the digital video
bus.
Reserved
00
01
10
11
00
01
10
11
Use to divide the frequency of
the sensors master clock input,
mclk to generate the internal
sensor clock, Hclk.
Program 00 Hex (the default) for
Hclk to equal mclk or divide
mclk by any number between 1
and FF Hex.
12 bit mode, bits
d[11:0] of the digital
video bus are active.
This is the default.
10 bit mode, bits
d[11:2] of the digital
video bus are active.
8 bit mode, bits
d[11:4] of the digital
video bus are active.
Reserved.
A/D [11:0] -> d[11:0].
A/D [10:0] -> d[11:1]
A/D [9:0] -> d[11:2]
A/D [8:0] -> d[11:3]
Description
Description
26
Register Name Digital Video Mode 1
Address
Mnemonic
Type
Reset Value
Register Name Digital Video Mode 2
Address
Mnemonic
Type
Reset Value
7
6
5
4
3
2
1
0
7:4
3:0
Bit
Bit
PixClkMode
VsyncMode
HsyncMode
PixClkPol
VsynPol
HsynPol
OddEvenEn
TriState
HsyncAdjust
Bit Symbol
Bit Symbol
07 Hex
VMODE1
Read/Write
00 Hext
08 Hex
VMODE2
Read/Write
00 Hex
Assert to set the pclk to “data
ready mode”. Clear, the default, to
set pclk to “free running mode”.
Assert to set the vsync pin to
“pulse mode”. Clear (the default)
to set the vsync signal to “level
mode”.
Assert to force the hsync signal to
pulse for a minimum of four pixel
clocks at the end of each row.
Clear (the default) to force the
hsync signal to a level indicating
valid data within a row.
Assert to set the active edge of
the pixel clock to negative. Clear
(the default) to set the active edge
of the clock to positive.
Assert to force the vsync signal to
generate a logic 0 during a frame
readout (Level Mode), or a nega-
tive pulse at the end of a frame
readout (Pulse Mode). Clear (the
default) to force the vsync signal
to generate a logic 1 during a
frame readout (Level Mode), or a
negative pulse at the end of a
frame readout (Pulse Mode).
Assert to force the hsync signal to
generate a logic 0 during a row
readout (Level Mode), or a nega-
tive pulse at the end of a row
readout (Pulse Mode). Clear (the
default) to force the hsync signal
to generate a logic 1 during a row
readout (Level Mode), or a nega-
tive pulse at the end of a readout
(Pulse Mode).
Assert to force the vsync pin to act
as an odd/even field indicator.
Clear (the default) to force the
vsync pin to act as a vertical syn-
chronization signal.
Assert to tri-state all output signals
(data and control) on the digital
video port. Clear (default) to
enable all signals (data and con-
trol) on the digital video port.
Use to program the leading edge
of hsync to the first valid pixel at
the beginning of each row. This
can be 0-hex to F-hex corre-
sponding to 0 - 15 pixel clocks.
Default 0.
Reserved
Description
Description
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