xr16v2651im Exar Corporation, xr16v2651im Datasheet - Page 36

• Manufacturer Part Number: xr16v2651im
• Description: High Performance Duart With 32-byte Fifo And Powersave
• Manufacturer: Exar Corporation

XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
EFR[5]: Special Character Detect Enable
•
•
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the selected trigger level and RTS de-
asserts HIGH at the next upper trigger level. RTS# will return LOW when FIFO data falls below the next lower
trigger level. The RTS# output must be asserted (LOW) before the auto RTS can take effect. RTS# pin will
function as a general purpose output when hardware flow control is disabled.
•
•
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
•
•
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see
4.14.1
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts HIGH.
Data transmission resumes when CTS# returns LOW.
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
Table
8.
36
REV. 1.0.2