isppac-clk5620v-01t48c Lattice Semiconductor Corp., isppac-clk5620v-01t48c Datasheet - Page 33

• Manufacturer Part Number: isppac-clk5620v-01t48c
• Description: In-system Programmable, Zero-delay Clock Generator With Universal Fan-out Buffer
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
User Electronic Signature
A user electronic signature (UES) feature is included in the E
32 bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory
control data. The specifics this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every ispClock5600 device to prevent unauthorized readout of
the E
bits in the device. This cell can only be erased by reprogramming the device, so the original configuration can not
be examined once programmed. Usage of this feature is optional. The specifics of this feature are discussed in the
IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer soft-
ware. Devices can then be ordered through the usual supply channels with the user’s specific configuration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
Evaluation Fixture
Included in the basic ispClock5600 Design Kit is an engineering prototype board that can be connected to the par-
allel port of a PC using a Lattice ispDOWNLOAD
ispClock5600 and can be used in real time to check circuit operation as part of the design process. Input and out-
put connections (SMA connectors for all RF signals) are provided to aid in the evaluation of the ispClock5600 for a
given application. (Figure 29).
Figure 29. Download from a PC
PAC-SYSTEMCLK5620
PACCLK5620-EV
2
CMOS configuration bit patterns. Once programmed, this cell prevents further access to the functional user
Part Number
PAC-Designer
Software
Complete system kit, evaluation board, ispDOWNLOAD cable and software.
Evaluation board only, with components, fully assembled.
®
cable. It demonstrates proper layout techniques for the
33
ispDownload
Cable (6')
2
CMOS memory of the ispClock5600. This consists of
Description
ispClock5600 Family Data Sheet
4
ispClock5600
Circuitry
System
Device
Other