isppac-clk5620v-01t48c Lattice Semiconductor Corp., isppac-clk5620v-01t48c Datasheet - Page 8

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isppac-clk5620v-01t48c

Manufacturer Part Number
isppac-clk5620v-01t48c
Description
In-system Programmable, Zero-delay Clock Generator With Universal Fan-out Buffer
Manufacturer
Lattice Semiconductor Corp.
Datasheet
Lattice Semiconductor
Output Test Loads
Figures 3-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and other
selected parameters as noted in the various tables of this data sheet.
Figure 3. CMOS Termination Load
Figure 4. HSTL/SSTL Termination Load
Figure 5. LVDS/LVPECL Termination Load
ispCLOCK
ispCLOCK
Zo = HSTL: ~20
50 /3"
50 /3"
ispCLOCK
SSTL: 40
50 /1"
50 /1"
Zo = 50
50 /3"
(parasitic)
33.2
33.2
(parasitic)
Interface Circuit
50 /3"
3pF
3pF
50 /36"
44.2
8
34
34
50 /36"
0.1U
0.1U
50
ispClock5600 Family Data Sheet
950
50 /36"
50 /36"
SCOPE
50
950
VTERM
5pF
ChA
ChB
SCOPE
50
SCOPE
5pF
50
50
5pF
5pF

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