isppac-powr6at6 Lattice Semiconductor Corp., isppac-powr6at6 Datasheet - Page 24

• Manufacturer Part Number: isppac-powr6at6
• Description: In-system Programmable Power Supply Monitoring And Margining Controller
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Finally, the individual lock status inputs all meet at a common NAND gate. A trim lock condition is generated when
all six trim status inputs are high causing the CLTLOCK/SMBA pin to go low. If the trim lock is lost for any monitored
trim output pin, the CLTLOCK/SMBA pin will de-assert (go open). This could be due to a failed power supply for
example, or if the ispPAC-POWR6AT6 can no longer adjust a controlled supply to specification. Interrogation of the
I
further diagnose an underlying fault.
There is an alternative path the CLTLOCK/SMBA signal can take, depending on how the ispPAC-POWR6AT6 has
been configured. Refer to the I
enabled in PAC-Designer, the trim lock result is first sent to the I
to the CLTLOCK/SMBA output pin. The purpose of this control logic is to make the CLTLOCK/SMBA signal work in
accordance with the SMBus Alert protocol. The main difference between the two output path alternatives is that
SMBus Alert stays set (low) until acknowledged by the host I
when a trim lock condition is achieved, as well as when it is lost. Either condition must be acknowledged or the
SMBus Alert condition will not go away. Note that on initial device power-on, or after an I
SMBus Alert is blocked (no trim lock). The SMBus master must explicitly set the CLT_LOCK_STATUS bit-6 low to
begin the SMBAlert process.
SMBus SMBAlert Function
The ispPAC-POWR6AT6 provides an SMBus SMBAlert function to request service from the bus master when used
as part of an SMBus system. When the SMBAlert signal mode for closed-loop trimming is chosen in PAC-Designer,
the CLTLOCK/SMBA output pin will go low whenever the trim lock condition status changes. The reason for this is
to report both when all outputs are in trim lock and when one or more trim output pins lose trim lock.
When a selected (unmasked) closed-loop trim output loses its locked status, servicing the resulting SMBus Alert
and interrogating the I
acknowledgement by the host I
CLTLOCK/SMBA trim status occurs.
After initial device turn-on and power-on reset (POR) is complete, the SMBA bit in the I
set high or “1”. The SMBAlert function of the ispPAC-POWR6AT6 is effectively suspended until this location has
been overwritten with a low or “0”. The purpose of this is to prevent output to the CLTLOCK/SMBA pin before the
bus master or host processor is ready to process SMBAlerts.
Note that if closed loop trimming is enabled and completes before this action is performed, the initial trim lock indi-
cation (as an SMBAlert) will not occur. If this happens, trim status can still be interrogated, however. Reading the
I
achieved. Otherwise, the CLTENb pin must be held high until after the I
afterwards to insure detection of the initial trim lock status with an SMBAlert.
After the SMBA bit has been set low, any subsequent change in trim lock status will be reported with an SMBAlert
output to the CLTLOCK/SMBA pin. To process an SMBAlert, the following steps must be performed to service the
alert and resume monitoring for the next change in trim lock status:
The typical flow for an SMBAlert transaction is as follows (Figure 22):
2
2
C register determines which trim output pin lost lock. Also, the ADC can be used to measure individual supplies to
C trim status register to see that all trim bits are high (bit-1 to bit-6) is a valid indication that trim lock has been
1. I
2. ispPAC-POWR6AT6 closed-loop trim control logic pulls the CLTLOCK/SMBA pin low
3. Master responds to interrupt from SMBA line
4. Master broadcasts a read operation by sending the SMBus Alert Response Address (ARA, 18h)
5. ispPAC-POWR6AT6 responds to the ARA request by transmitting its device address
ever the trim lock status changes
2
C closed loop trim register SMBA bit is forced to high by internal ispPAC-POWR6AT6 control logic when-
2
C closed-loop trim register will reveal which trim output pin(s) that are involved. After
2
C/SMBus control logic box shown in Figure 21. When the alternative output path is
2
C processor, the CLTLOCK/SMBA pin will be de-asserted until another change in
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2
C processor. Also, an SMBus Alert is set (pulled low)
2
C/SMBus control logic for processing before going
2
C SMBA bit is written low and then enabled
ispPAC-POWR6AT6 Data Sheet
2
C register (0x00, bit-6) is
2
C software reset, an