isppac-powr6at6 Lattice Semiconductor Corp., isppac-powr6at6 Datasheet - Page 27

• Manufacturer Part Number: isppac-powr6at6
• Description: In-system Programmable Power Supply Monitoring And Margining Controller
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
of the ispPAC-POWR6AT6 JTAG interface follows. For complete details of the reference specification, refer to the
publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990 (which now
includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the isp-
PAC-POWR6AT6. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct
sequence, instructions are shifted into an instruction register, which then determines subsequent data input, data
output, and related operations. Device programming is performed by addressing the configuration register, shifting
data in, and then executing a program configuration instruction, after which the data is transferred to internal
2
E
CMOS cells. It is these non-volatile cells that store the configuration or the ispPAC-POWR6AT6. A set of instruc-
tions are defined that access all data registers and perform other internal control operations. For compatibility
between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are func-
tionally specified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by
the manufacturer. The two required registers are the bypass and boundary-scan registers. Figure 25 shows how
the instruction and various data registers are organized in an ispPAC-POWR6AT6.
Figure 25. ispPAC-POWR6AT6 TAP Registers
CFG_DATA REGISTER (56 BITS)
2
E
CMOS
NON-VOLATILE
MEMORY
CFG_ADDRESS REGISTER (5 BITS)
UES REGISTER (32 BITS)
IDCODE REGISTER (32 BITS)
BYPASS REGISTER (1 BIT)
INSTRUCTION REGISTER (8 BITS)
TEST ACCESS PORT (TAP)
OUTPUT
LOGIC
LATCH
TDI
TCK
TMS
TDO
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether
an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a
small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as
shown in Figure 26. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO)
becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-
Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But
there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a
reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on
default state.
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