isppac20 Lattice Semiconductor Corp., isppac20 Datasheet - Page 28

• Manufacturer Part Number: isppac20
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Serial Port Programming Interface
Communication with the ispPAC20 is facilitated via an
IEEE 1149.1 test access port (TAP). It is used by the
ispPAC20 as a serial programming interface, and not for
boundary scan test purposes. There are no boundary
scan logic cells in the ispPAC20 architecture. This does
not prevent the ispPAC20 from functioning correctly,
however, when placed in a valid serial chain with other
IEEE 1149.1 compliant devices.
A brief description of the ispPAC20 serial interface fol-
lows. For complete details of the reference specification,
refer to the publication, Standard Test Access Port and
Boundary-Scan Architecture, IEEE Std 1149.1-1990
(which now includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the
control interface for serially accessing the digital I/O of
the ispPAC20. The TAP controller is a state machine
driven with mode and clock inputs. Under the correct
protocol, instructions are shifted into an instruction regis-
ter which then determines subsequent data input, data
output, and related operations. Device programming is
performed by addressing the user register, shifting data
in, and then executing a program user instruction, after
which the data is transferred to internal E
is these non-volatile cells that determine the configura-
tion of the ispPAC20. By cycling the TAP controller
through the necessary states, data can also be shifted
Figure 16. ispPAC20 TAP Registers
IEEE Standard 1149.1 Interface
TDI
TCK
Test Access Port
(TAP) Logic
Instruction Register
Bypass Register
User Register
TMS TRST
ID Register
Output
Latch
2
TDO
CMOS cells. It
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out of the user register to verify the current ispPAC20
configuration. Instructions exist to access all data regis-
ters and perform internal control operations.
For compatibility between compliant devices, two data
registers are mandated by the IEEE 1149.1 specification.
Others are functionally specified, but inclusion is strictly
optional. Finally, there are provisions for optional data
registers defined by the manufacturer. The two required
registers are the bypass and boundary-scan registers.
For ispPAC20, the bypass register is a 1-bit shift register
that provides a short path through the device when
boundary testing or other operations are not being per-
formed. The ispPAC20, as mentioned, has no
boundary-scan logic and therefore no boundary scan
register. All instructions relating to boundary scan opera-
tions place the ispPAC20 in the BYPASS mode to maintain
compliance with the specification. The optional identifi-
cation register described in IEEE 1149.1 is also included
in the ispPAC20. One additional data register included in
the TAP of the ispPAC20 is the Lattice-defined user
register. Figure 16 shows how the instruction and various
data registers are placed in an ispPAC20.
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test
Mode Select (TMS) inputs. These inputs determine
whether an Instruction Register or Data Register opera-
tion is performed. Driven by the TCK input, the TAP
consists of a small 16-state controller design. In a given
state, the controller responds according to the level on
the TMS input as shown in Figure 17. Test Data In (TDI)
and TMS are latched on the rising edge of TCK, with Test
Data Out (TDO) becoming valid on the falling edge of
TCK. There are six steady states within the controller:
Test-Logic-Reset, Run-Test/Idle, Shift-Data-Register,
Pause-Data-Register, Shift-Instruction-Register, and
Pause-Instruction-Register. But there is only one steady
state for the condition when TMS is set high: the Test-
Logic-Reset state. This allows a reset of the test logic
within five TCKs or less by keeping the TMS input high.
Test-Logic-Reset is the power-on default state.
When the correct logic sequence is applied to the TMS
and TCK inputs, the TAP will exit the Test-Logic-Reset
state and move to the desired state. The next state after
Test-Logic-Reset is Run-Test/Idle. Until a data or instruc-
tion scan is performed, no action will occur in Run-Test/
Idle (steady state = idle). After Run-Test/Idle, either a
data or instruction scan is performed. The states of the
Data and Instruction Register blocks are identical to each
other differing only in their entry points. When either block
Specifications ispPAC20