a54sx16p Actel Corporation, a54sx16p Datasheet
a54sx16p
Available stocks
Related parts for a54sx16p
a54sx16p Summary of contents
Page 1
... See the Actel website for the latest version of the datasheet. v3.2 ™ A54SX16P A54SX32 16,000 32,000 24,000 48,000 1,452 2,880 924 1,800 528 1,080 175 249 3 3 Yes Yes Yes – ...
Page 2
... SX Family FPGAs Ordering Information P 2 A54SX16 – Blank = Not PCI Compliant P = PCI Compliant Part Number A54SX08 = 12,000 System Gates A54SX16 = 24,000 System Gates A54SX16P = 24,000 System Gates A54SX32 = 48,000 System Gates Plastic Device Resources PLCC Device 84-Pin A54SX08 69 A54SX16 – A54SX16P – ...
Page 3
... Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 3 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 PCI Compliance for the SX Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 A54SX16P AC Specifications for (PCI Operation 1-10 A54SX16P DC Specifications (3.3 V PCI Operation 1-12 A54SX16P AC Specifications (3.3 V PCI Operation 1-13 Power-Up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 Power-Down Sequencing ...
Page 4
...
Page 5
SX Family FPGAs General Description The Actel SX family of FPGAs features a sea-of-modules architecture that delivers device performance and integration levels not currently achieved by any other FPGA architecture. SX devices greatly simplify design time, enable dramatic reductions in ...
Page 6
SX Family FPGAs The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals (Figure registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional Routing Tracks ...
Page 7
Chip Architecture The SX family chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications. Module Organization Actel has arranged all C-cell and ...
Page 8
SX Family FPGAs Routing Resources Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within clusters and SuperClusters (Figure 1-5 of ...
Page 9
DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring R- cell in a given SuperCluster. DirectConnect uses a hardwired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less ...
Page 10
SX Family FPGAs Boundary Scan Testing (BST) All SX devices are IEEE 1149.1 compliant. SX devices offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. These functions are controlled through the special test pins ...
Page 11
... Device should not be operated outside the Recommended Operating Conditions the A54SX16P must be greater than or equal to V CCR operation. 3. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than V 0 less than GND – ...
Page 12
SX Family FPGAs Table 1-4 • Recommended Operating Conditions Parameter Temperature Range* 3.3 V Power Supply Tolerance 5.0 V Power Supply Tolerance Note: *Ambient temperature ( used for commercial and industrial; case temperature (T A Table 1-5 • ...
Page 13
... PCI Compliance for the SX Family The SX family supports 3.3 V and 5.0 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. Table 1-6 • A54SX16P DC Specifications (5.0 V PCI Operation) Symbol Parameter V Supply Voltage for Array CCA V Supply Voltage required for Internal Biasing CCR V Supply Voltage for I/Os ...
Page 14
... SX Family FPGAs A54SX16P AC Specifications for (PCI Operation) Table 1-7 • A54SX16P AC Specifications for (PCI Operation) Symbol Parameter I Switching Current High OH(AC) (Test Point) I Switching Current High OL(AC) (Test Point) I Low Clamp Current CL slew Output Rise Slew Rate R slew Output Fall Slew Rate F Notes: 1. Refer to the V/I curves in Figure 1-9 on page of that specified here ...
Page 15
... Figure 1-9 shows the 5.0 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P device. 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 –0.05 PCI I Mininum OH –0.10 –0.15 –0.20 Figure 1-9 • 5.0 V PCI Curve for A54SX16P Device I = 11.9 × (V – 5.25) × OUT OUT for V > V > 3 OUT PCI I ...
Page 16
... SX Family FPGAs A54SX16P DC Specifications (3.3 V PCI Operation) Table 1-8 • A54SX16P DC Specifications (3.3 V PCI Operation) Symbol Parameter V Supply Voltage for Array CCA V Supply Voltage required for Internal Biasing CCR V Supply Voltage for I/Os CCI V Input High Voltage IH V Input Low Voltage Input Pull-up Voltage ...
Page 17
... A54SX16P AC Specifications (3.3 V PCI Operation) Table 1-9 • A54SX16P AC Specifications (3.3 V PCI Operation) Symbol Parameter Condition Switching Current High 0 < V 0.3V I OH(AC) 0.7V (Test Point) V Switching Current High V 0.6V I OL(AC) 0.18V (Test Point Low Clamp Current –3 < High Clamp Current –3 < slew Output Rise Slew Rate 0 ...
Page 18
... SX Family FPGAs Figure 1-10 shows the 3.3 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P device. 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0. –0.05 PCI I Minimum OH –0.10 –0.15 –0.20 Figure 1-10 • 3.3 V PCI Curve for A54SX16P Device I = (98.0/V ) × (V – × OUT CC for V > V > 0 ...
Page 19
... Note: No inputs should be driven (high or low) before completion of power-up. Power-Down Sequencing Table 1-11 • Power-Down Sequencing V V CCA CCR A54SX08, A54SX16, A54SX32 3.3 V 5.0 V A54SX16P 3.3 V 3.3 V 3.3 V 5.0 V 3.3 V 5.0 V Note: No inputs should be driven (high or low) after the beginning of the power-down sequence. V Power-Up Sequence CCI 3 ...
Page 20
SX Family FPGAs Evaluating Power in SX Devices A critical element of system reliability is the ability of electronic devices to safely dissipate the heat generated during operation. The thermal characteristics of a circuit depend on the device and package ...
Page 21
... The design 0.615 0.615 utilized 100 percent of the dedicated flip-flops 140 A54SX16P device. A pattern of 0101… was clocked into the device at frequencies ranging from 1 MHz to 138 171 200 MHz. Shifting in a series of 0101… caused 50 percent 138 ...
Page 22
SX Family FPGAs Step 1: Define Terms Used in Formula Module Number of logic modules switching at f (Used 50%) m Average logic modules switching rate f (MHz) (Guidelines: f/10) m Module capacitance C (pF) EQM Input Buffer Number of ...
Page 23
Figure 1-11 shows the characterized power dissipation numbers for the shift register design using frequencies ranging from 1 MHz to 200 MHz. 1200 1000 800 600 400 200 Figure 1-11 • Power Dissipation Junction Temperature (T ) ...
Page 24
SX Family FPGAs Table 1-15 • Package Thermal Characteristics Package Type Plastic Leaded Chip Carrier (PLCC) Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP) Very Thin Quad Flatpack (VQFP) Plastic Quad Flat Pack (PQFP) without Heat Spreader Plastic ...
Page 25
SX Timing Model Input Delays I/O Module t = 1.5 ns INY t = 0.5 ns SUD Routed Clock t = 1.5 ns (100% Load) RCKH F = 250 MHz MAX Hardwired Clock t = ...
Page 26
SX Family FPGAs GND 50% 50 Out 1 DLH DHL Figure 1-13 • Output Buffer Delays Load 1 (used to measure propagation delay) To Output Under Test 35 pF Figure ...
Page 27
Register Cell Timing Characteristics D t SUD CLK Q CLR PRESET Figure 1-17 • Flip-Flops Timing Characteristics Timing characteristics for SX devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input characteristics are common to all SX family members. ...
Page 28
SX Family FPGAs A54SX08 Timing Characteristics Table 1-17 • A54SX08 Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect DC ...
Page 29
Table 1-17 • A54SX08 Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) HCKL t Minimum ...
Page 30
SX Family FPGAs A54SX16 Timing Characteristics Table 1-18 • A54SX16 Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect DC ...
Page 31
Table 1-18 • A54SX16 Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) HCKL t Minimum ...
Page 32
... SX Family FPGAs A54SX16P Timing Characteristics Table 1-19 • A54SX16P Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect Routing Delay, Fast Connect Routing Delay RD1 ...
Page 33
... Table 1-19 • A54SX16P Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) HCKL t Minimum Pulse Width HIGH HPWH t Minimum Pulse Width LOW HPWL t Maximum Skew ...
Page 34
... SX Family FPGAs Table 1-19 • A54SX16P Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description TTL/PCI Output Module Timing t Data-to-Pad LOW to HIGH DLH t Data-to-Pad HIGH to LOW DHL t Enable-to-Pad ENZL t Enable-to-Pad ENZH t Enable-to-Pad ENLZ t Enable-to-Pad ...
Page 35
A54SX32 Timing Characteristics Table 1-20 • A54SX32 Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect ...
Page 36
SX Family FPGAs Table 1-20 • A54SX32 Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) ...
Page 37
Pin Description CLKA/B Clock A and B These pins are 3 5.0 V PCI/TTL clock inputs for clock distribution networks. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set ...
Page 38
...
Page 39
Package Pin Assignments 84-Pin PLCC Figure 2-1 • 84-Pin PLCC (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html 84-Pin PLCC v3.2 54SX Family FPGAs 2-1 ...
Page 40
Family FPGAs 84-Pin PLCC A54SX08 Pin Number Function 1 V CCR 2 GND 3 V CCA 4 PRA, I/O 5 I CCI 8 I/O 9 I/O 10 I/O 11 TCK, I/O 12 TDI, I/O 13 ...
Page 41
PQFP 208 1 Figure 2-2 • 208-Pin PQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. 208-Pin PQFP v3.2 54SX Family FPGAs 2-3 ...
Page 42
... V 48 CCI CCI I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I CCR GND CCA GND 64 I/O 65* I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 I/O 72 v3.2 208-Pin PQFP A54SX16, A54SX08 A54SX16P A54SX32 Function Function Function I/O I/O I/O I/O I/O I/O NC I/O I CCI CCI CCI CCA CCA CCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O GND GND GND ...
Page 43
... I/O 129 I/O 130 I/O 131 I/O 132 I/O 133 V 134 CCI CCI I/O 135 I/O 136 I/O 137 I/O 138 TDO, I/O 139 I/O 140 GND 141 I/O 142 I/O 143 I/O 144 v3.2 54SX Family FPGAs 208-Pin PQFP A54SX16, A54SX08 A54SX16P A54SX32 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCA CCA CCA CCI CCI CCI NC I/O I/O I/O I/O I/O I/O I/O ...
Page 44
... CCI CCI I/O 201 I/O 202 I/O 203 I/O 204 I/O 205 I/O 206 I/O 207 I/O 208 I/O I/O I/O I/O I/O I/O I/O CLKA v3.2 208-Pin PQFP A54SX16, A54SX08 A54SX16P A54SX32 Function Function Function CLKB CLKB CLKB CCR CCR CCR GND GND GND CCA CCA CCA GND GND GND PRA, I/O PRA, I/O PRA, I/O I/O I/O ...
Page 45
TQFP 144 1 Figure 2-3 • 144-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. 144-Pin TQFP v3.2 54SX Family FPGAs 2-7 ...
Page 46
... CCI CCI GND 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I CCR CCR V 56 CCA CCA I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 GND CCI CCI V 66 CCA CCA I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 GND 72 v3.2 144-Pin TQFP A54SX08 A54SX16P A54SX32 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCI CCI CCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O PRB, I/O PRB, I/O I/O I/O I/O ...
Page 47
... CCR I/O 127 V I/O 128 GND I/O 129 V I/O 130 I/O 131 PRA, I/O I/O 132 I/O 133 V 134 CCA GND 135 I/O 136 GND 137 V 138 CCI I/O 139 I/O 140 I/O 141 I/O 142 I/O 143 I/O 144 TCK, I/O v3.2 54SX Family FPGAs 144-Pin TQFP A54SX16P A54SX32 Function Function GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCI CCI CCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 48
Family FPGAs 176-Pin TQFP 176 1 Figure 2-4 • 176-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html 176-Pin TQFP v3.2 ...
Page 49
... I/O 41 I/O 42 I/O 43 TMS CCI I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 GND CCA GND 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 I/O 64 PRB, I/O I CCI V 67 CCA I/O 68 v3.2 54SX Family FPGAs 176-Pin TQFP A54SX16, A54SX16P A54SX32 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCI CCI CCI I/O I/O I/O NC I/O I/O ...
Page 50
... TDO, I/O 121 I/O 122 GND 123 I/O 124 I/O 125 I/O 126 I/O 127 I/O 128 I/O 129 I/O 130 I/O 131 V 132 CCA V 133 CCI CCI I/O 134 I/O 135 I/O 136 v3.2 176-Pin TQFP A54SX16, A54SX08 A54SX16P A54SX32 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND CCA CCA CCA GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 51
... V 160 CCI I/O 161 I/O 162 I/O 163 I/O 164 I/O 165 I/O 166 I/O 167 I/O 168 I/O 169 I/O 170 I/O 171 CLKA 172 CLKB 173 V 174 CCR GND 175 V 176 TCK, I/O CCA v3.2 54SX Family FPGAs 176-Pin TQFP A54SX16, A54SX16P A54SX32 Function Function PRA, I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I CCI CCI ...
Page 52
Family FPGAs 100-Pin VQFP 100 1 Figure 2-5 • 100-Pin VQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html 100-Pin VQFP v3.2 ...
Page 53
... I/O I/O 55 I/O I/O 56 I/O I CCA CCA CCI CCI 59 I/O I/O 60 I/O I/O 61 I/O I/O 62 I/O I/O 63 I/O I/O 64 I/O I/O 65 I/O I/O 66 I/O I CCA CCA 68 GND GND v3.2 54SX Family FPGAs 100-Pin VQFP A54SX16, Pin A54SX08 A54SX16P Number Function Function 69 GND GND 70 I/O I/O 71 I/O I/O 72 I/O I/O 73 I/O I/O 74 I/O I/O 75 I/O I/O 76 I/O I/O 77 I/O I/O 78 I/O I/O 79 I/O I/O 80 I/O I/O 81 I/O I CCI CCI 83 I/O I/O 84 I/O I/O 85 I/O I/O ...
Page 54
Family FPGAs 313-Pin PBGA ...
Page 55
PBGA 313-Pin PBGA Pin A54SX32 Pin Number Function Number A1 GND AC5 A3 NC AC7 A5 I/O AC9 A7 I/O AC11 A9 I/O AC13 A11 I/O AC15 A13 V AC17 CCR A15 I/O AC19 A17 I/O AC21 A19 I/O ...
Page 56
Family FPGAs 313-Pin PBGA Pin A54SX32 Number Function Number H20 I/O H22 V CCI H24 I/O J1 I/O J3 I I/O J11 I/O J13 CLKA J15 I/O J17 I/O J19 I/O J21 GND J23 ...
Page 57
PBGA Figure 2-7 • 329-Pin PBGA (Top View) Note For Package Manufacturing and ...
Page 58
Family FPGAs 329-Pin PBGA Pin A54SX32 Number Function Number A1 GND AA13 A2 GND AA14 A3 V AA15 CCI A4 NC AA16 A5 I/O AA17 A6 I/O AA18 A7 V AA19 CCI A8 NC AA20 A9 I/O AA21 A10 ...
Page 59
PBGA 329-Pin PBGA Pin A54SX32 Pin Number Function Number D3 I/O F22 D4 TCK, I/O F23 I/O G20 D10 I/O G21 D11 V G22 CCA D12 ...
Page 60
Family FPGAs 329-Pin PBGA Pin A54SX32 Number Function Number T22 I/O T23 I/O U1 I CCA U4 I/O U20 I/O U21 V CCA U22 I/O U23 I CCI V2 I/O V3 I/O 2 ...
Page 61
FBGA Figure 2-8 • 144-Pin FBGA (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html ...
Page 62
Family FPGAs 144-Pin FBGA Pin A54SX08 Number Function Number A1 I/O A2 I/O A3 I CCA A6 GND A7 CLKA A8 I/O A9 I/O A10 I/O A11 I/O A12 I/O B1 I/O B2 GND B3 ...
Page 63
... Table 1-1 was updated. Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definitions of these categories are as follows: ...
Page 64
... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court Dunlop House, Riverside Way Mountain View, CA Camberley, Surrey GU15 3YL 94043-4655 USA United Kingdom Phone 650.318.4200 Phone +44 (0) 1276 401 450 Fax 650 ...