ht82m72e Holtek Semiconductor Inc., ht82m72e Datasheet - Page 23

• Manufacturer Part Number: ht82m72e
• Description: Ht82m72e/ht82m72a -- Rf One Channel Mouse 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

more cycles. If the wake-up results in the execution of
the next instruction following the HALT instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
Watchdog Timer
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown lo-
cations, due to certain uncontrollable external events
such as electrical noise. It operates by providing a de-
vice reset when the WDT counter overflows. The WDT
clock is supplied by its own internal dedicated internal
WDT oscillator. Note that if the WDT configuration op-
tion has been disabled, then any instruction relating to
its operation will result in no operation.
All Watchdog Timer options, such as enable/disable,
WDT clock source and clear instruction type all selected
through configuration options. There are no internal reg-
isters associated with the WDT in this device. However,
it should be noted that this specified internal clock pe-
riod can vary with VDD, temperature and process varia-
tions. Whether the WDT clock source is its own internal
WDT oscillator, it is further divided by an internal 6-bit
counter and a clearable single bit counter to give longer
Rev. 1.20
Watchdog Timer Register
Watchdog Timer
23
Watchdog time-outs. As the clear instruction only resets
the last stage of the divider chain, for this reason the ac-
tual division ratio and corresponding Watchdog Timer
time-out can vary by a factor of two.
The exact division ratio depends upon the residual value
in the Watchdog Timer counter before the clear instruc-
tion is executed. It is important to realise that as there
are no independent internal registers or configuration
options associated with the length of the Watchdog
Timer time-out, it is completely dependent upon the fre-
quency the internal WDT oscillator.
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. How-
ever, if the system is in the Power Down Mode, when a
WDT time-out occurs, the TO bit in the status register
will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to
clear the contents of the WDT. The first is an external
hardware reset, which means a low level on the RES
pin, the second is using the watchdog software instruc-
tions and the third is via a HALT instruction.
There are only CLR WDT instruction to clear the Watch-
dog Timer.
HT82M72E/HT82M72A
May 22, 2008