ht82v842a Holtek Semiconductor Inc., ht82v842a Datasheet
ht82v842a
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ht82v842a Summary of contents
Page 1
... Black level neutralizer, target setting: 16~127LSB · Built-in serial interface General Description The HT82V842A is a CMOS single-chip signal process- ing device for CCD area sensors. It consists of a clamp circuit, Correlated Double Sampler (CDS), Programma- ble Gain Amplifier (PGA), reference voltage generator, Block Diagram Rev ...
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... ADC sampling clock input I Reference sampling pulse input I Data sampling pulse input Pulse input for ADIN clamp and black calibration control. I Clamp control input. I Blanking pulse input No connection I Black level period pulse input I Serial clock input I Serial data input 2 HT82V842A January 2, 2006 ...
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... =20MHz S 3V CCDIN input =1MHz IN ADIN input =1MHz Absolute gain 3V 3V Relative gain 3V 3V Absolute gain 3V Relative gain HT82V842A Ta=25 C Min. Typ. Max. Unit 0. 0. 200 1.1 P-P V 1.0 P-P 1.5 1 ...
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... Although black level codes CAL Test Conditions Min. V Conditions DD 3.0V 0.5 3.0V 50 3.0V 3.0V 3.0V 23 3.0V 23 3.0V 11 3.0V 11 3.0V 3.0V 3.0V 2 3.0V 5 3.0V 1 3.0V 10 3.0V 10 3.0V 0 3.0V 10 3.0V Active High-Z 3.0V High-Z Active 3.0V 4 HT82V842A Typ. Max. Unit LSB 0.6 1 1.4 1.55 V 1.65 1.75 V 1.15 1.25 V 127 LSB 127 LSB 1 LSB V =0V, Ta= Typ. Max. Unit 20 MHz ...
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... The DC clamping (CCDCLP) is allowed while the OBP pin is low. The black level cancellation is available at ADIN signal to PGA mode. The black level cancella- tion is available at the ADCLP period in this mode. The clamping function and black level canceling function are done simultaneously. 5 HT82V842A January 2, 2006 ...
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... High-speed Black Level Cancellation The HT82V842A has a high speed black level cancella- tion function, which by means of a register setting en- hances the settling speed within a fixed period from access to the serial interface. It increases the gain of the setting DAC within a fixed period and in turn increases the charge/discharge current to the OBCAP capacitor ...
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... HT82V842A prohibited to write to a non-defined ad- dress. When a data length is below 16 bits, the data is not executed. Registers The HT82V842A has 10 bits 7 registers that control the operations. All registers are write only, the serial regis- ters are written by the serial interface. 7 HT82V842A ...
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... CDS gain control/Black loop gain boost/Boost period PGA gain ADC code at black level (1 LSB step) Register Map ------ ------ ------ ------------------------------------------------------------------------ 8 HT82V842A ------ ------ --------------------------- January 2, 2006 ...
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... Monitor off 0 1 CDS signal to monitor 1 0 PGA output monitor 1 1 Output REFIN and CCDIN 0 0 CDS gain=odB 0 1 CDS gain=6.02dB 1 0 CDS gain=12.04dB 1 1 CDS gain= 1.94dB 0 Boost control on 1 Always high gain 9 HT82V842A Operations January 2, 2006 ...
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... HT82V842A Operations HEX PGA Gain (dB 0.046 2 0.093 3 0.142 4 0.187 3E 2.915 3F 2.962 40 3.011 41 3.056 7F 5.972 80 6.021 81 6.058 C0 9.031 FF 11.994 100 12 ...
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... HT82V842A Black Code HEX Forbidden January 2, 2006 ...
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... ADCK inversion: At Mode 1 register D6=1; 6.0 clk delay In ADIN input mode, the above mentioned register setting is available. At ADIN (PGA) input Mode 1 register D5=0 and D4=1, digital data output is delayed by 2 clks. ADCK Clock Waveform Rev. 1.00 ADC Direct Input Chart OUTCK Timing Chart 12 HT82V842A January 2, 2006 ...
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... SCK, CS Falling Time Period F SNUM Number of Serial Data Data Output Sequence Pixel Data Readout Sequence (1): Start of Conversion Rev. 1.00 Test Conditions Min. VDD Conditions 3.0V 3.0V 40 3.0V 40 3.0V 20 3.0V 20 3.0V 30% 70% 3.0V 70% 30% 3.0V Serial I/F Timing Chart 13 HT82V842A V =0V, Ta= Typ. Max. Unit 10 MHz pcs January 2, 2006 ...
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... Pixel Data Readout Sequence (2): End of Conversion Clock Timing Variations by Register Setting Clock timing variations when it is inverted by register settings. No inversion Mode 1 register D6=0, Mode 2 register D2=0; Default Pulse Control (Default: No Inversion) Rev. 1.00 14 HT82V842A January 2, 2006 ...
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... Mode 1 register D6=1, Mode 2 register D2=0 SHR & SHD inversion Mode 1 register D6=0, Mode 2 register D2=1 Pulse Control (SHR & SHD Inversion) ADCK, SHR & SHD inversion Mode 1 register D6=1, Mode 2 register D2=1 Pulse Control (ADCK, SHR & SHD Inversion) Rev. 1.00 Pulse Control (ADCK Inversion) 15 HT82V842A January 2, 2006 ...
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... Application Circuits Note: * Pin 18 can also connect to ground with a 4.7k resistor. ** The capacitor connects to OBCAP pin maybe need adjust by user s applications from 0.1 F~1 F typically. Rev. 1.00 16 HT82V842A January 2, 2006 ...
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... Package Information 48-pin LQFP (7´7) Outline Dimensions Symbol Rev. 1.00 Dimensions in mm Min. Nom. 8.90 6.90 8.90 6.90 0.50 0.20 1.35 0.10 0.45 0. HT82V842A Max. 9.10 7.10 9.10 7.10 1.45 1.60 0.75 0.20 7 January 2, 2006 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 18 HT82V842A January 2, 2006 ...