as7c331mntf18a Alliance Memory, Inc, as7c331mntf18a Datasheet

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as7c331mntf18a

Manufacturer Part Number
as7c331mntf18a
Description
3.3v Flowthrough Synchronous Sram With
Manufacturer
Alliance Memory, Inc
Datasheet
Logic block diagram
Selection guide
December 2004
Features
• Organization: 1,048,576 words × 18 bits
• NTD
• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP package
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
12/23/04, v 1.2
architecture for efficient bus operation
3.3V 1M x 18 Flowthrough Synchronous SRAM with NTD
A[19:0]
CE0
CE1
CE2
ADV / LD
DQ [a,b]
BWb
BWa
R/W
LBO
ZZ
CLK
CEN
20
18
D
D
Control
burst logic
Address
register
register
logic
CLK
input
Data
CLK
Alliance Semiconductor
275
-75
8.5
7.5
90
60
CLK
Q
Q
20
OE
• Individual byte write and global write
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
18
D
addr. registers
CLK
Write delay
®
250
-85
8.5
10
80
60
Q
OE
18
CLK
Output
18
buffer
DQ [a,b]
18
20
1M x 18
SRAM
array
18
Copyright © Alliance Semiconductor. All rights reserved.
AS7C331MNTF18A
230
-10
12
10
80
60
TM
DDQ
P. 1 of 18
Units
mA
mA
mA
ns
ns

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as7c331mntf18a Summary of contents

Page 1

... D Write delay addr. registers CLK Control logic CLK 18 18 Data D Q input register CLK OE -75 -85 8.5 10 7.5 8.5 275 250 Alliance Semiconductor AS7C331MNTF18A TM DDQ Q 20 CLK SRAM array Output buffer [a,b] -10 Units 230 ...

Page 2

... Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD- Alliance Semiconductor AS7C331MNTF18A Speed 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/ ...

Page 3

... DQb5 DDQ V 21 SSQ DQb6 22 DQb7 23 24 DQPb SSQ V 27 DDQ 12/23/04, v 1.2 ® TQFP 14 x 20mm Alliance Semiconductor AS7C331MNTF18A DDQ 76 V SSQ DQPa 73 DQa7 72 DQa6 V 71 SSQ 70 V DDQ 69 DQa5 68 DQa4 V ...

Page 4

... Functional Description The AS7C331MNTF18A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory (SRAM) organized as 1,048,576 words × 18 bits and incorporates a LATE Write. This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD write operation that improves bandwidth over flowthrough burst devices normal flowthrough burst device, the write data, command, and address are all applied to the device on the same clock edge ...

Page 5

... DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. PUS 12/23/04, v 1.2 ® Description or left floating, device follows interleaved Burst order. When DD is guaranteed after the time t is met. After entering SNOOZE MODE, all inputs except ZZ SB2 ZZI Alliance Semiconductor AS7C331MNTF18A . The duration of SB2 ...

Page 6

... External NOP/WRITE ABORT (Begin Burst) High Next Current enables WRITEs to byte “b” (DQb pins). Alliance Semiconductor AS7C331MNTF18A Linear burst order (LBO = ...

Page 7

... T –65 bias Symbol Min Nominal V 3.135 3 3.135 3.3 DDQ Vss 0 0 Symbol Min Nominal V 3.135 3 2.375 2.5 DDQ Vss 0 0 Alliance Semiconductor AS7C331MNTF18A Max Unit +4 0 0.5 V DDQ 1 +150 C o +135 C Max Unit 3.465 V 3.465 Max Unit 3 ...

Page 8

... < Max Deselected < 0.2V, I SB1 ≤ 0.2V or ≥ V all ≥ V Deselected Max I SB2 ≤ ≥ V all Alliance Semiconductor AS7C331MNTF18A Min Max Unit -2 2 µA DD < µA DDQ +0.3 DDQ -0.3** 0 ...

Page 9

... CSH t 2.0 – 2.0 CENS t 0.5 – 0.5 CENH t 2.0 – 2.0 ADVS t 0.5 – 0.5 ADVH Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C331MNTF18A -10 1 Min Max Unit Notes – 12 – ns – – 4.0 ns – 2.5 – ns 2,3,4 – 3.0 – – 0 – ns 2,3,4 – 4.0 ns 2,3,4 – 4.0 ...

Page 10

... Falling input HZOE OE Q(A1) Q(A2) Q(A2Y‘01) Read Continue Continue Continue Q(A2) Read Read Q(A2Y‘10) Q(A2Y‘01) Q(A2Y‘11) Alliance Semiconductor AS7C331MNTF18A Undefined t CYC A3 Q(A2Y‘10) Q(A3) Q(A2Y‘11) Continue Inhibit Read Read Read Clock Q(A3) Q(A3Y‘01 HLZC ...

Page 11

... HZOE Dout Q(n-2) Q(n-1) Write DSEL D(A1) 12/23/04, v 1.2 ® D(A1) D(A2) D(A2Y‘01) Write Continue Continue Continue D(A2) Write Write Write D(A2Y‘10) D(A2Y‘01) D(A2Y‘11) Alliance Semiconductor AS7C331MNTF18A t CYC D(A3) D(A2Y‘10) D(A2Y‘11) Continue Inhibit Write Write Clock D(A3) D(A3Y‘01 ...

Page 12

... Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. BW[a:d] is don’t care. 12/23/04, v 1.2 ® LZC OH D(A1) D(A2) Q(A3) D(A2Ý01) Burst Burst Read Read Write Read Q(A3) Q(A4) D(A2Ý01) Q(A4Ý01) Alliance Semiconductor AS7C331MNTF18A t CYC HZC D(A5) Q(A6) Q(A4) Q(A4Ý01) t HZOE t LZOE Write Read Write D(A5) Q(A6) D(A7 DSEL ...

Page 13

... Address A1 D/Q Command Read Burst Q(A1) Q(A1Ý01) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low low. 12/23/04, v 1.2 ® A2 Q(A1Ý01) Q(A1) Q(A1Ý10) STALL Burst DSEL Burst Q(A1Ý10) DSEL Alliance Semiconductor AS7C331MNTF18A A3 D(A2) Burst Write Write Burst NOP NOP D(A2) D(A2Ý10) D(A2Ý01) D(A3 ...

Page 14

... Timing waveform of snooze mode CLK ZZ setup cycle ZZ t ZZI I supply I SB2 All inputs Deselect or Read Only (except ZZ) Dout 12/23/04, v 1.2 ® t PUS ZZ recovery cycle t RZZI Deselect or Read Only High-Z Alliance Semiconductor AS7C331MNTF18A Normal operation Cycle ...

Page 15

... L for 3.3V I/ DDQ for 2.5V I/O Figure B: Output load (A) at any given temperature and voltage. LZC IL Alliance Semiconductor AS7C331MNTF18A Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319Ω/1667Ω D OUT 5 pF* 353Ω/1538Ω GND *including scope and jig capacitance Figure C: Output load(B) ...

Page 16

... Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters 12/23/04, v 1.2 ® Alliance Semiconductor AS7C331MNTF18A b e α ...

Page 17

... Ordering information Package &Width AS7C331MNTF18A-75TQC TQFP x18 AS7C331MNTF18A-75TQI Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts (Ex. AS7C331MNTF18A-85TQCN) Part numbering guide AS7C Alliance Semiconductor SRAM prefix 2. Operating voltage 3.3V 3. Organization NTF = No Turn-Around Delay. Flow-through mode 5 ...

Page 18

... Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C331MNTF18A ® Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C331MNTF18A Document Version: v 1.2 ...

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