as7c33256pfs18b ETC-unknow, as7c33256pfs18b Datasheet - Page 16

• Manufacturer Part Number: as7c33256pfs18b
• Manufacturer: ETC-unknow

AC test conditions
Notes
1
2
3
4
5
6
7
8
12/10/04; v.1.7
+3.0V
GND
• Output load: see Figure B, except for t
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
For test conditions, see AC Test Conditions, Figures A, B, C.
This parameter measured with output load condition in Figure C.
This parameter is sampled, but not 100% tested.
t
tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs
must meet the setup and hold times for all rising edges of CLK when chip is enabled.
Write refers to
Chip select refers to
HZOE
Figure A: Input waveform
10%
90%
is less than t
GWE, BWE, BW[a,b].
LZOE
CE0, CE1, CE2
; and t
90%
10%
HZC
is less than t
D
OUT
LZC
LZC
Figure B: Output load (A)
, t
Alliance Semiconductor
at any given temperature and voltage.
LZOE
Z
0
= 50Ω
, t
HZOE
, t
HZC
50Ω
30 pF*
, see Figure C.
V
®
L
for 3.3V I/O;
= V
for 2.5V I/O
= 1.5V
DDQ
/2
353Ω / 1538Ω
D
OUT
Figure C: Output load (B)
AS7C33256PFS18B
Thevenin equivalent:
319Ω / 1667Ω
5 pF*
GND
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
*including scope
and jig capacitance
P. 16 of 19